A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8x8 mesh network-on-chip in 45nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 110-111

  Anders, Mark A ^a   Kaul, Himanshu ^a   Hsu, Steven K ^a   Agarwal, Amit ^a   Mathew, Sanu K ^a   Sheikh, Farhana ^a   Krishnamurthy, Ram K ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BISECTION BANDWIDTH; CIRCUIT-SWITCHED NETWORKS; DATA INTERCONNECT; DATA STORAGE; DATA WIDTH; DYNAMIC OPTIMIZATION; ENERGY EFFICIENT; HIGH BANDWIDTH; HIGH THROUGHPUT; INTERCONNECT NETWORKS; LOW ENERGIES; LOW LATENCY; LOW-VOLTAGE; MAXIMUM THROUGH-PUT; MESH NETWORK; METAL-GATE; MULTI-CORE PROCESSOR; NETWORK POWER; PACKET-SWITCHED; POWER SAVINGS; RE-CONFIGURABLE; ROUTE DATA; SCALABLE PERFORMANCE; STREAMING TRAFFIC; SWITCHED CHANNELS; TRAFFIC PATTERN;

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DATA TRANSFER; DATA TRANSFER RATES; MESH NETWORKING; MICROPROCESSOR CHIPS; OPTICAL COMMUNICATION; OPTIMIZATION; PACKET NETWORKS; ROUTERS; SWITCHING CIRCUITS; TELECOMMUNICATION SYSTEMS; THROUGHPUT; VLSI CIRCUITS;

ENERGY EFFICIENCY;

EID: 77952175242     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5434078     Document Type: Conference Paper

References (4)

1. S. Bell et al., "TILE64 - Processor: A 64-Core SoC with Mesh Interconnect," ISSCC, pp. 88-89, 2008.
2. M. Taylor et al., "A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network," ISSCC, pp. 170-171, 2003.
3. M. Anders et al., "A 2.9Tb/s 8W 64-Core Circuit-switched Network-on-Chip in 45nm CMOS," ESSCIRC, pp. 182-185, 2008.
4. K. Mistry et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," IEDM, pp. 247-250, 2007.