A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS

ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Volumn , Issue , 2008, Pages 182-185

  Anders, Mark ^a   Kaul, Himanshu ^a   Hansson, Martin ^a   Krishnamurthy, Ram ^a   Borkar, Shekhar ^a  

^a INTEL RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); SWITCHING CIRCUITS; SWITCHING NETWORKS; TRANSMISSIONS;

CORE CIRCUITS; PIPELINED CIRCUITS; POWER CONSUMPTIONS; RANDOM DATUMS; SWITCHED NETWORKS;

COUPLED CIRCUITS;

EID: 58049111166     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2008.4681822     Document Type: Conference Paper

References (9)

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