Spurious -tone suppression techniques applied to a wide-bandwidth 2.4GHz fractional-N PLL

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 342-344

  Wang, Kevin J ^a   Swaminathan, Ashok ^b   Galton, Ian ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NextWave Wireless Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH;

DELTA SIGMA MODULATOR; FRACTIONAL SPURS; FRACTIONAL-N PLL; LOOP FILTER; REFERENCE SPUR; SPURIOUS TONES; SUPPRESSION TECHNIQUE; WIDE BANDWIDTH;

PHASE LOCKED LOOPS;

EID: 49549084183     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523197     Document Type: Conference Paper

References (7)

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2. A. Swaminathan et al., "A Wide-Bandwidth 2.4GHz ISM-Band FractionalN " PLL with Adaptive Phase-Noise Cancellation," IEEE J. Solid-State Circuits, pp. 2639-2650, Dec. 2007.
3. S. Pellerano et al., "A Dual-Band Frequency Synthesizer for 802.11a/b/g with Fractional-Spur Averaging Technique," ISSCC Dig. Tech. Papers, pp. 104-105, Feb. 2005.
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5. A. Swaminathan et al., "A Digital Requantizer with Shaped Requantization Noise that Remains Well Behaved after Non-linear Distortion," IEEE T. Sig. Proc., pp. 5382-5394, Nov. 2007.
6. B. Zhang et al., "A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-μm CMOS," IEEE J. Solid-State Circuits, pp. 855-865, June 2003.
7. A. Maxim, "A Low -86dBc Reference Spurs 1-5 GHz 0.13μm CMOS Frequency Synthesizer PLL Using a Fully-Dual-Path Sampled Feed-Forward Loop Filter Architecture," IEEE J. Solid-State Circuits, pp. 2503-2514, Nov. 2007.