Window-masked segmented digital clock manager-FPGA-based digital pulsewidth modulator technique

IEEE Transactions on Power Electronics

Volumn 24, Issue 11, 2009, Pages 2649-2660

  Batarseh, Majd Ghazi ^a   Al Hoor, Wisam ^a   Huang, Lilly ^b   Iannello, Chris ^a   Batarseh, Issa ^a  

^a University of Central Florida   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

DC DC converters; Digital control; Digital power electronics; Digital pulsewidth modulators (DPWM); Field programmable gate arrays

Indexed keywords

DIGITAL CLOCK MANAGERS; DIGITAL CLOCKS; DIGITAL CONTROL; DIGITAL MODULATORS; DUTY CYCLES; FPGA BOARDS; LOWER-POWER CONSUMPTION; PHASE-SHIFTING; PULSE WIDTH MODULATORS; SWITCHING PERIOD;

ARCHITECTURE; DC POWER TRANSMISSION; DC-DC CONVERTERS; DIGITAL CONTROL SYSTEMS; LOGIC GATES; MANAGEMENT; MANAGERS; MODULATORS; POWER ELECTRONICS; PULSE WIDTH MODULATION; SIGNAL RECEIVERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77952113729     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2009.2033066     Document Type: Article

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