A segmented digital pulse width modulator with self-calibration for low-power SMPS

2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Volumn , Issue , 2005, Pages 367-370

  Trescases, Olivier ^a   Wei, Guowen ^a   Ng, Wai Tung ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DC-DC CONVERTERS; DIGITAL CIRCUITS; PHASE LOCKED LOOPS; TIME DELAY;

DELAY LOCKED LOOPS; DELAY SEGMENTS; DIGITAL PULSE WIDTH MODULATOR (DPWM);

PULSE WIDTH MODULATION;

EID: 43549120453     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2005.1635283     Document Type: Conference Paper

References (9)