Spacer gate lithography for reduced variability due to line edge roughness

IEEE Transactions on Semiconductor Manufacturing

Volumn 23, Issue 2, 2010, Pages 311-315

  Sun, Xin ^a   Liu, Tsu Jae King ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Line edge roughness (LER); Scalability; Spacer lithography; Variability

Indexed keywords

3D DEVICE SIMULATION; BULK-SI MOSFET; GATE LITHOGRAPHY; GATE-LENGTH; LINE EDGE ROUGHNESS; LINE EDGE ROUGHNESS (LER); SIMULATION RESULT; SPACER LITHOGRAPHY; TRANSISTOR PERFORMANCE;

ELECTRON BEAM LITHOGRAPHY; PHOTORESISTS; SCALABILITY; SEMICONDUCTING SILICON COMPOUNDS;

ROUGHNESS MEASUREMENT;

EID: 77951981572     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2010.2046050     Document Type: Conference Paper

References (8)

1. A. Asenov, "Simulation of statistical variability in nano MOSFETs," in Symp. VLSI Tech. Dig., 2007, pp. 86-87.
2. A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I. Mizushima, K. Okano, H. Kawasaki, S. Inaba, T. Izumida, T. Kanemura, N. Aoki, K. Ishimaru, H. Ishiuchi, K. Suguro, K. Eguchi, and Y. Tsunashima, "Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15 nm FinFET with elevated source/drain extension," in IEDM Tech. Dig., 2005, pp. 863-866.
3. R. Rooyackers, E. Augendre, B. Degroote, N. Collaert, A. Nackaerts, A. Dixit, T. Vandeweyer, B. Pawlak, M. Ercken, E. Kunnen, G. Dilliway, F. Leys, R. Loo, M. Jurczak, and S. Biesemans, "Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency," in IEDM Tech. Dig., 2006, pp. 993-996.
4. "Sentaurus User's Manual," Synposys Inc., Parsippany, NJ, 2006, ver. 2006.06.
5. Y.-K. Choi, T.-J. King, and C. Hu, "A spacer patterning technology for nanoscale CMOS," IEEE Trans. Electron Devices, vol.49, no.3, pp. 436-441, Mar. 2002. (Pubitemid 34404841)
6. "Matlab User's Manual," MathWorks Inc., Natick, MA, 2002, Ver. 6.5.
7. "Update," Int. Technol. Roadmap for Semiconductors, 2006.
8. M. Miyamura, T. Fukai, T. Ikezawa, R. Ueno, K. Takeuchi, and M. Hane, "SRAM critical yield evaluation based on comprehensive physical/statistical modeling, considering anomalous non-Gaussian intrinsic transistor fluctuations," in Symp. VLSI Tech. Dig., 2007, pp. 22-23.