Bit matrix multiplication in commodity processors

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2008, Pages 7-12

  Hilewitz, Yedidya ^a   Lauradoux, Cédric ^a   Lee, Ruby B ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC SYSTEMS; HARDWARE COSTS; INTERNATIONAL CONFERENCES;

SUPERCOMPUTERS; VECTORS;

MATRIX ALGEBRA;

EID: 51649098779     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2008.4580146     Document Type: Conference Paper

References (25)

1. T. M. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. IEEE Computer, 35(2):59-67, 2002.
2. E. Biham. A Fast New DES Implementation in Software. In Fast Software Encryption - FSE '97, pages 260-272, 1997.
3. J. Burke, J. McDonald, and T. M. Austin. Architectural Support for Fast Symmetric-Key Cryptography. In Architectural Support for Programming Languages and Operating Systems, ASPLOS 2000, pages 178-189. ACM, 2000.
4. Cray Inc. Cray Assembly Language (CAL) for Cray X1 Systems Reference Manual, version 1.2. Cray Inc., 2003.
5. Cray, Inc. CRAY/MTA Principles of Operation, 2005.
6. K. Diefendorff, P. K. Dubey, R. Hochsprung, and H. Scales. AltiVec Extension to PowerPC Accelerates Media Processing. IEEE Micro, 20(2):85-95, 2000.
7. Y. Hilewitz and R. B. Lee. Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions. In IEEE International Conference on Application-Specific Systems, Architecture and Processors, pages 65-72, 2006.
8. Intel. Intel 64 and IA-32 Architectures Software Developers Manual Volume 2b: Instruction Set Reference, N-Z. Intel Corporation, 2006.
9. M. Kowarschik and C. Weiß. An Overview of Cache Optimization Techniques and Cache-Aware Numerical Algorithms. In Algorithms for Memory Hierarchies, Lecture Notes in Computer Science 2625, pages 213-232, 2002.
10. C. Lauradoux. From Hardware to Software Synthesis of Linear Feedback Shift Registers. In Proceedings of Workshopon Performance Optimization for High-Level Languages and Libraries - POHLL 2007, Mar. 2007.
11. R. B. Lee. Accelerating Multimedia with Enhanced Microprocessors. IEEE Micro, 15(2):22-32, 1995.
12. R. B. Lee. Subword parallelism with MAX-2. IEEE Micro, 16(4):51-59, 1996.
13. R. B. Lee, Z. Shi, and X. Yang. Efficient permutation instructions for fast software cryptography. IEEE Micro, 21(6):56-69, 2001.
14. R. B. Lee, Z. Shi, and X. Yang. How a Processor can Permute s bits in O(1) cycles. In Proceedings of Hot Chips 14, Aug. 2002.
15. W. Lee, G. J. Geissler, S. J. Johnson, and A. J. Schiffleger. Vector Bit-Matrix Multiply Function Unit, 1996.
16. C. Lemuet, J. Sampson, J.-F. Collard, and N. Jouppi. The potential energy efficiency of vector acceleration. In ACM/IEEE conference on Supercomputing - SC '06, page 77. ACM, 2006.
17. S. Lin and D. J. Costello. Error Control Coding, Second Edition. Prentice-Hall, Inc., 2004.
18. L.Soulé. Parallel Logic Simulation: An Evaluation of Centralized-Time and Distributed-Time Algorithms. PhD thesis, Stanford University, 1992.
19. U. Manber. Introduction to Algorithms: A Creative Approach. Addison-Wesley, 1989.
20. C. Paar. Efficient VLSI Architectures for Bit Parallel Computation in Galois Fields. PhD thesis, Universität GH Essen, 1994.
21. Z. Shi, X. Yang, and R. B. Lee. Arbitrary Bit Permutations in One or Two Cycles. In Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pages 237-247, June 2003.
22. Taiwan Semiconductor Manufacturing Corporation. TCBN90GTHP: TSMC 90nm Core Library Databook, version 1.1, 2006.
23. Texas Instrument. TMS320C64x Technical Overview, 2001.
24. H. C. van Tilborg. Encyclopedia of Cryptography and Security. Springer-Verlag, 2005.
25. M. Wei, M. Snir, J. Torrellas, and R. B. Tremaine. A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads. In Watson Conference on Interaction between Architecture, Circuits, and Compilers, 2005.