Efficient scheduling of nested parallel loops on multi-core systems

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2009, Pages 74-83

  Kejariwal, Arun ^a   Nicolau, Alexandru ^a   Veidenbaum, Alexander V ^a   Banerjee, Utpal ^a   Polychronopoulos, Constantine D ^b  

^a University of California   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE BEHAVIOR; CACHE MISS; COMPILER TECHNIQUES; EFFICIENT SCHEDULING; EXECUTION TIME; FORTRAN; GENERAL APPROACH; INDUSTRY-STANDARD BENCHMARKS; ITERATION SPACES; MULTI-CORE SYSTEMS; PARALLEL EXECUTIONS; PARALLEL LOOPS; PERFORMANCE BOTTLENECKS;

PROFITABILITY; PROGRAM COMPILERS; SCHEDULING;

MICROPROCESSOR CHIPS;

EID: 77951449939     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2009.19     Document Type: Conference Paper

References (38)

1. Wine. http://sourceforge.net/project/showfiles.php? group id=6241.
2. A. Kejariwal, H. Saito, X. Tian, M. Girkar, U. Banerjee, A. Nicolau, and C. D. Polychronopoulos. A general approach for partitioning n-dimensional parallel nested loops with conditionals. In Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, pages 49-58, Cambridge, MA, 2006.
3. C. Polychronopoulos. Loop coalescing: A compiler transformation for parallel machines. In Proceedings of the 1987 International Conference on Parallel Processing, pages 235- 242, August 1987.
4. A. Kejariwal, A. Nicolau, U. Banerjee, A. V. Veidenbaum, and C. D. Polychronopoulos. Cache-aware iteration space partitioning. In Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pages 269-270, Salt Lake City, UT, 2008.
5. J. Hennessy and D. Patterson. Computer Architecture A Quantitative Approach. Morgan Kaufmann Publishers, San Mateo, CA, 1990.
6. Y. Liu, Z. Zhang, R. Qiao, and R. Ju. A region-based compilation infrastructure. In Proceedings of the 7th Workshop on Interaction between Compilers and Computer Architecture, 2003.
7. T. Suganuma, T. Yasue, and T. Nakatani. A region-based compilation technique for a Java just-in-time compiler. SIGPLAN Notices, 38(5):312-323, 2003.
8. TMPerformance Analyzer 8.0.1 for Windows. http://www.intel.com/cd/software/products/asmo-na/eng/vtune/219898.htm.
9. OpenBSD. http://www.openbsd.org/.
10. K. Yoshizoe, T. Matsumoto, and K. Hiraki. Speculative parallel execution on JVM. In Proceedings of 1st U.K. Workshop on Java for High Performance Network Computing, 1998.
11. S. Wang, X. Dai, K. S. Yellajyosula, A. Zhai, and P.-C. Yew. Loop selection for thread-level speculation. In Proceedings of the 18th International Workshop on Languages and Compilers for Parallel Computing, Hawthorne, NY, October 2005.
12. SPEC CFP2000. http://www.spec.org/cpu2000/CFP2000.
13. M. J. Wolfe. High Performance Compilers for Parallel Computing. Addison-Wesley, Redwood City, CA, 1996.
14. A. J. C. Bik. The Software Vectorization Handbook: Applying Multimedia Extensions for Maximum Performance. Intel Press, Hilsboro, OR, 2004.
15. OpenMP Specification, version 2.5. http://www.openmp.org/drupal/mp- documents/spec25.pdf.
16. W.-D. Weber and A. Gupta. Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: Preliminary results. In Proceedings of the 16th Annual International Symposium on Computer Architecture, pages 273-280, Jerusalem, Israel, 1989.
17. R. Thekkath and S. J. Eggers. The effectiveness of multiple hardware contexts. In Proceedings of the sixth International Conference on Architectural Support for Programming Languages and Operating Systems, pages 328-337, San Jose, CA, 1994.
18. A. Kejariwal, P. D'Alberto, A. Nicolau, and C. D. Polychronopoulos. A geometric approach for partitioning Ndimensional non-rectangular iteration spaces. In Proceedings of the 17th International Workshop on Languages and Compilers for Parallel Computing, pages 102-116, West Lafayette, IN, 2004.
19. S. Ghosh and M. Montonosi amd S. Malik. Cache miss equations: An analytical representation of cache misses. In Proceedings of the 11th ACM International Conference on Supercomputing, pages 317-324, Vienna, Austria, July 1997.
20. J. S. Harper, D. J. Kerbyson, and G. R. Nudd. Analytical modeling of set-associative cache behavior. IEEE Transactions on Computers, 48(10):1009-1024, 1999.
21. S. Chatterjee, E. Parker, P. J. Hanlon, and A. R. Lebeck. Exact analysis of the cache behavior of nested loops. In Proceedings of the SIGPLAN '01 Conference on Programming Language Design and Implementation, pages 286-297, Snowbird, UT, 2001.
22. B. B. Fraguela, R. Doallo, J. Touri no, and E. L. Zapata. A compiler tool to predict memory hierarchy performance of scientific codes. Parallel Computing, 30(2):225-248, 2004.
23. Intel®Compilers for Linux http://www.intel.com/cd/software/ products/asmo-na/eng/compilers/284264.htm.
24. D. A. Padua and M. J. Wolfe. Advanced compiler optimizations for supercomputers. Communications of the ACM, 29(12):1184-1201, December 1986.
25. F. Irigoin and R. Triolet. Supernode partitioning. In Proceedings of the Fifteenth Annual ACM Symposium on the Principles of Programming Languages, San Diego, CA, January 1988.
26. J. Sheu and T. Thai. Partitioning and mapping nested for-loops on multiprocessor systems. In Proceedings of the 1991 ACM International Conference on Supercomputing, Cologne, Germany, June 1991.
27. J.-P. Sheu and T.-S. Chen. Partitioning and mapping of nested loops for linear array multicomputers. Journal of Supercomputing, 9(1-2):183-202, 1995.
28. I. Drositis, G. Goumas, N. Koziris, P. Tsanakas, and G. Papakonstantinou. Evaluation of loop grouping methods based on orthogonal projection spaces. In Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing, pages 469-476, August 2000.
29. M. R. Haghighat and Constantine D. Polychronopoulos. Symbolic analysis for parallelizing compilers. ACM Transactions on Programming Languages and Systems, 18(4):477-518, July 1996.
30. R. Sakellariou. On the Quest for Perfect Load Balance in Loop-Based Parallel Computations. PhD thesis, Department of Computer Science, University of Manchester, October 1996.
31. C. Polychronopoulos, D. J. Kuck, and D. A. Padua. Execution of parallel loops on parallel processor systems. In Proceedings of the 1986 International Conference on Parallel Processing, pages 519-527, August 1986.
32. E. H. D'Hollander. Partitioning and labeling of loops by unimodular transformations. IEEE Transactions on Parallel and Distributed Systems, 3(4):465-476, 1992.
33. A. Kejariwal, A. Nicolau, U. Banerjee, and C. D. Polychronopoulos. A novel approach for partitioning iteration spaces with variable densities. In Proceedings of the 10th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pages 120-131, Chicago, IL, 2005.
34. Z. Guz, I. Keidar, A. Kolodny, and U. Weiser. Nahalal: Cache organization for chip multiprocessors. IEEE Computer Architecture Letters, 6(1), 2007.
35. G. Ammons, T. Ball, and J. R. Larus. Exploiting hardware performance counters with flow and context sensitive profiling. In Proceedings of the SIGPLAN '97 Conference on Programming Language Design and Implementation, pages 85-96, 1997.
36. F. Schneider and T. Gross. Using platform-specific performance counters for dynamic compilation. In Proceedings of the 18th International Workshop on Languages and Compilers for Parallel Computing, Hawthorne, NY, October 2005.
37. F. Schneider, M. Payer, and T. Gross. Online optimizations driven by hardware performance monitoring. In Proceedings of the SIGPLAN '07 Conference on Programming Language Design and Implementation, 2007.
38. NetBSD. http://www.netbsd.org/.