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Volumn , Issue , 2008, Pages 402-405

Design and measurements of SEU tolerant latches

Author keywords

[No Author keywords available]

Indexed keywords

ADJACENT NODES; CHARGE SHARING; DICE LATCH; DUAL INTERLOCKED STORAGE CELLS; LAYOUT CONSIDERATIONS; MEASUREMENTS OF; SINGLE EVENT UPSETS;

EID: 77951190173     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (20)

References (7)
  • 1
    • 84884190839 scopus 로고    scopus 로고
    • Technical design report, 1, CERN-LHCC-97-016; inner tracker: Technical design report
    • ATLAS Collaboration
    • ATLAS Collaboration, Inner Tracker "Technical Design Report, 1, CERN-LHCC-97-016; Inner Tracker: Technical Design Report,", 2, CERN-LHCC-97-017
    • CERN-LHCC-97-017 , vol.2
    • Tracker, I.1
  • 3
    • 84884201085 scopus 로고    scopus 로고
    • ATLAS pixel detector upgrade: A study of a prototype readout chip manufactured in 0.13 μm technology
    • Master thesis presented at Lund, Sweden March
    • D. Hallberg "ATLAS Pixel Detector Upgrade: A study of a prototype readout chip manufactured in 0.13 μm technology," Master thesis presented at Lund Institute of Technology, Lund, Sweden March 2005
    • (2005) Lund Institute of Technology
    • Hallberg, D.1
  • 4
    • 77951202979 scopus 로고    scopus 로고
    • Development of the ATLAS FE-I4 pixel readout IC for b-layer upgrade and super-LHC
    • submitted to
    • M. Karagounis et al. "Development of the ATLAS FE-I4 pixel readout IC for b-layer Upgrade and Super-LHC," submitted to TWEPP 2008
    • (2008) TWEPP
    • Karagounis, M.1
  • 5
    • 0030375853 scopus 로고    scopus 로고
    • Upset hardened memory by design for submicron CMOS technology
    • Dec.
    • T. Calin, M. Nicolaidis, R. Velazco, "Upset Hardened Memory by Design for Submicron CMOS technology," IEEE Trans. Nucl. Sci., Vol. 43, pp. 2874-2878, Dec. 1996
    • (1996) IEEE Trans. Nucl. Sci. , vol.43 , pp. 2874-2878
    • Calin, T.1    Nicolaidis, M.2    Velazco, R.3
  • 6
    • 33144457627 scopus 로고    scopus 로고
    • HBD layout isolation techniques for multiple node charge collection mitigation
    • Dec
    • J.D. Black et al. "HBD Layout Isolation Techniques for Multiple Node Charge Collection Mitigation," IEEE Trans. Nucl. Sci., Vol. 52, pp. 2536-2541, Dec.2005
    • (2005) IEEE Trans. Nucl. Sci. , vol.52 , pp. 2536-2541
    • Black, J.D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.