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Volumn , Issue , 2008, Pages 70-75

Development of the ATLAS FE-I4 pixel readout IC for b-layer Upgrade and Super-LHC

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN BLOCKS; DESIGN GOAL; DESIGN WORK; HIGHER INTEGRATION; HYBRID PIXEL DETECTORS; PIXEL READOUT; RADIATION TOLERANCES; TRIPLE WELL;

EID: 77951202979     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (15)

References (15)
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    • Barbero, M.1
  • 7
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    • Design and measurements of SEU tolerant latches
    • submitted to
    • M. Menouni et al., Design and measurements of SEU tolerant latches, submitted to TWEPP proceedings (2008)
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    • Menouni, M.1
  • 9
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    • LVDS I/O interface for gb/s-per-pin operation in 0.35-μm CMOS
    • A. Boni et al., LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS, IEEE JSSC Vol. 36 NO. 4 (2001)
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  • 10
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    • J. Tyhach et al., A 90-nm FPGA I/O Buffer Design With 1.6-Gb/s Data Rate for Source-Synchronous System and 300-MHz Clock Rate for External Memory Interface, IEEE JSSC Vol. 40 NO. 9 (2005)
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    • Tyhach, J.1
  • 11
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    • A low-voltage, low quiescent current, low drop-out regulator
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  • 12
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  • 14
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    • A capacitor charge pump DC-DC converter for physics instrumentation
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.