Hardware architecture and FPGA implementation of a parallel elitism-based compact genetic algorihm

IEEE Region 10 Annual International Conference, Proceedings/TENCON

Volumn , Issue , 2009, Pages

  Jewajinda, Yutana ^a   Chongstitvatana, Prabhas ^b  

^a NATIONAL ELECTRONICS AND COMPUTER TECHNOLOGY CENTER   (Thailand)

^b CHULALONGKORN UNIVERSITY   (Thailand)

Author keywords

FPGA; Genetic algorithms; Hardware

Indexed keywords

BENCH-MARK PROBLEMS; COMPACT GENETIC ALGORITHM; FPGA; FPGA IMPLEMENTATIONS; HARDWARE ARCHITECTURE; PARALLEL GENETIC ALGORITHMS; PERFORMANCE IMPROVEMENTS; PROBABILITY MODELS; SCALABLE HARDWARE ARCHITECTURE;

ELECTRIC CONDUCTIVITY MEASUREMENT; GENETIC ALGORITHMS; HARDWARE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 77951104811     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TENCON.2009.5396138     Document Type: Conference Paper

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