A hardware implementation of the compact genetic algorithm

Proceedings of the IEEE Conference on Evolutionary Computation, ICEC

Volumn 1, Issue , 2001, Pages 624-629

  Aporntewan, C ^a   Chongstitvatana, P ^a  

^a CHULALONGKORN UNIVERSITY   (Thailand)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SOFTWARE; COMPUTER WORKSTATIONS; FIELD PROGRAMMABLE GATE ARRAYS;

COMPACT GENETIC ALGORITMS;

GENETIC ALGORITHMS;

EID: 0034869196     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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3. Optimizing deceptive function with the SG-clans algorithm
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5. The compact genetic algorithm
6. Linkage learning via probabilistic modeling in the ECGA
7. Parallel random number generation for VLSI systems using cellular automata
8. A gate-level EHW chip: Implementing GA operations and reconfigurable hardware on a single LSI
9. HGA: A hardware-based genetic algorithm
10. An FPGA-based genetic algorithm machine
11. Implementing a genetic algorithm on a parallel custom computing machine
12. Multi-GAP: Parallel and distributed genetic algorithms in VLSI