Nano-magnet based ultra-low power logic design using non-majority gates

2009 9th IEEE Conference on Nanotechnology, IEEE NANO 2009

Volumn , Issue , 2009, Pages 870-873

  Augustine, Charles ^a   Behin Aein, Behtash ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DESIGN APPROACHES; MAJORITY GATES; NARROW GAP; PERFORMANCE METRICES; POWER; ULTRA-LOW POWER;

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; MAGNETS; NANOTECHNOLOGY;

MAJORITY LOGIC;

EID: 77950968374     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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