3D-LSI technology for image sensor

Journal of Instrumentation

Volumn 4, Issue 3, 2009, Pages

  Motoyoshi, Makoto ^a   Koyanagi, Mitsumasa ^a,b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b TOHOKU UNIVERSITY   (Japan)

Author keywords

HPDs, others); Manufacturing; Photon detectors for UV; Visible and IR photons (vacuum) (photomultipliers

Indexed keywords

CHIP SIZE PACKAGE; CMOS IMAGE SENSOR; ELEMENTARY TECHNOLOGIES; HIGH-SPEED IMAGE SENSORS; HPDS, OTHERS); PERFORMANCE DEGRADATION; PHOTON DETECTOR; THROUGH-SILICON-VIA (TSV);

DIGITAL CAMERAS; IMAGE SENSORS; MANUFACTURE; PHOTONS; PIXELS; SUPPLY CHAINS; TECHNOLOGY;

THREE DIMENSIONAL;

EID: 71049146289     PISSN: 17480221     EISSN: 17480221     Source Type: Journal    
DOI: 10.1088/1748-0221/4/03/P03009     Document Type: Article

References (25)

1. R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous and A.R. LeBlanc 1974 Design of ion-implanted MOSFET's with very small physical dimensions, IEEE J. Solid State Circuits 9 256, http://ieeexplore.ieee.org/xpl/freeabs-all.jsp? isnumber=22538&arnumber=1050511&count=21&index=11
2. G. Moore 1998 Cramming more components onto integrated circuits, Proc. IEEE 86 82
3. J. Stern and V. Ozguz 2007 Beyond 3D Integration: 3D Systems, Technical Digest of the International 3D System Integration Conference, 12.1-12.17
4. B. Haba Wafer-Level Stacking: Novel Approach to Stacking Very Thin Die, Conference on 3-D Architecture for Semiconductor Integration and Packaging, Oct. 2007
5. F. Carson Fan-in PoP: Enabling Smaller Form Factor 3D Integration, Conference on 3-D Architecture for Semiconductor Integration and Packaging, Oct. 2007
6. M. Robinson Bridging the Gap to TSV, Conference on 3-D Architecture for Semiconductor Integration and Packaging, Oct. 2007
7. A. Fazzi et al. 2005 A 0.14 mAW/Gbps High-Density Capacitive Interface for 3D system Integration, Proceedings of IEEE CICC, pg. 101-104
8. K. Kanda et al. 2003 A 1.27 Gb/s/ch 3mW/pin Wireless Superconnect (WSC) Interface Scheme, IEEE ISSCC Digest of Technical Papers, pg. 142-143
9. M. Bonkohara 1999 Japan activities in 1999,Electronic System-Integration Technology, Proceedings of 6th Ann. KGD Industrial Workshop, session II-3
10. M. Koyanagi 1989 Roadblocks in Achieving Three-Dimensional LSI, Extended Abst. 8th Symposium on Future Electron Devices, pg. 50-60
11. H. Takata et al. 1991 A Novel Fabrication Technology for Optically Interconnected Three-Dimensional LSI by Wafer Aligning and Bonding Technique, Extended Abst. 1991 Int'l Semiconductor Device Research Symposium, pg. 327-330
12. M. Koyanagi et al. 1998 New Three Dimensional Integration Technology for Future System-on-Silicon LSIs, IEEE Int'l Workshop on Chip Package Co-Design, pg. 96-103
13. M. Koyanagi, H. Kurino, K.W. Lee, K. Sakuma, N. Miyakawa and H. Itani 1998 Future System-on-Silicon LSI Chips, IEEE MICRO 18 17
14. H. Kurino et al. 1999 Intelligent Image Sensor Chip with Three Dimensional Structure, IEEE IEDM Technical Digest, pg. 879-882
15. K.W. Lee et al. 2000 Three-Dimensional shared memory fabricated using wafer stacking technology, IEEE IEDM Technical Digest, pg. 165-168
16. T. Ono et al. 2002 Three-dimensional processor system fabricating by wafer stacking technology, Proc. Int. Symp. Low-Power and High-Speed Chips, pg. 186-193
17. M. Motoyoshi, K. Kamibayashi, M. Bonkohara and M. Koyanagi 3D-LSI and Its Key Supporting Technologies, Technical Digest on 3D Architecture for Semiconductor Integration and Packaging, Nov. 2006
18. M. Bonkohara, M. Motoyoshi, K. Kamibayashi and M. Koyanagi 2007 Three dimensional LSI integration technology by Cchip on chip,'' ''chip on wafer'' and ''wafer on wafer'' with system in a package, Mater. Res. Soc. Symp. Proc. 970 35
19. M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka and H. Kurino 2006 Three-Dimensional Integration Technology Based on Wafer Bonding with Vertical Buried Interconnections, IEEE Trans. Elec. Dev. 53 2799
20. M. Motoyoshi, K. Kamibayashi, M. Bonkohara and M. Koyanagi 2007 Current and Future 3 Dimensional LSI Technologies, Technical Digest of the International 3D System Integration Conference, 8.1-8.14
21. M. Motoyoshi, H. Nakamura, K. Kamibayashi, M. Bonkohara and M. Koyanagi 2008 Future prospect of 3D-LSI processes, Technical Digest of the International 3D System Integration Conference, pg. 373-374
22. W. Suntharalingam et al. 2005 Megapixel CMOS Image Sensor Fabricated in Three-Dimensional Integrated Circuit Technology, ISSCC Dig. Tech. Papers 1 356
23. C. Keast et al. 2007 Three-Dimensional Integration Technology for Advanced Focal Planes, Digest of the International 3D System Integration Conference, 3.1-3.16
24. D. Temple et al. 2007 3-D Process Technologies for Highly Integrated Microsystems, Technical Digest of the International 3D System Integration Conference, 4.1-4.12
25. T. Fukushima et al. 2007 New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on Wafer Bonding Technique, IEEE IEDM Technical Digest, pg. 985-988