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Volumn , Issue , 2009, Pages 1156-1159

A low-power high-gain LNA for the 60 GHz band in a 65 nm CMOS technology

Author keywords

[No Author keywords available]

Indexed keywords

1DB COMPRESSION POINT; 60 GHZ BAND; 65NM CMOS TECHNOLOGY; BUILDING BLOCKES; BULK CMOS; CASCODE; CMOS RADIO; DIE AREA; HIGH-GAIN LNA; LOW POWER; LUMPED ELEMENT; MATCHING NETWORKS; PEAK GAIN; SIMULATED NOISE; ST MICROELECTRONICS; SUPPLY CURRENTS; SUPPLY VOLTAGES; TWO STAGE;

EID: 77950673325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APMC.2009.5384406     Document Type: Conference Paper
Times cited : (25)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.