A low-power high-gain LNA for the 60 GHz band in a 65 nm CMOS technology

APMC 2009 - Asia Pacific Microwave Conference 2009

Volumn , Issue , 2009, Pages 1156-1159

  Kraemer, Michael ^a   Dragomirescu, Daniela ^a,b   Plana, Robert ^a,b  

^a LAAS CNRS   (France)

^b UNIVERSITÉ PAUL SABATIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

1DB COMPRESSION POINT; 60 GHZ BAND; 65NM CMOS TECHNOLOGY; BUILDING BLOCKES; BULK CMOS; CASCODE; CMOS RADIO; DIE AREA; HIGH-GAIN LNA; LOW POWER; LUMPED ELEMENT; MATCHING NETWORKS; PEAK GAIN; SIMULATED NOISE; ST MICROELECTRONICS; SUPPLY CURRENTS; SUPPLY VOLTAGES; TWO STAGE;

AUDIO FREQUENCY AMPLIFIERS; LOW NOISE AMPLIFIERS; MICROELECTRONICS; MICROWAVES; NOISE FIGURE;

CMOS INTEGRATED CIRCUITS;

EID: 77950673325     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APMC.2009.5384406     Document Type: Conference Paper

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