New look-up-table optimizations for memory-based multiplication

ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings

Volumn , Issue , 2009, Pages 663-666

  Meher, Pramod Kumar ^a  

^a INSTITUTE FOR INFOCOMM RESEARCH   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ANTI-SYMMETRIC; AREA OVERHEAD; DELAY PRODUCT; DESIGN COMPILER; DIGITAL SIGNALS; EFFICIENT IMPLEMENTATION; HIGH-PRECISION; LOOK-UP-TABLE; LUT SIZE; SMALL INPUTS; SYNOPSYS;

CHEMICAL PLANTS; COST REDUCTION; INTEGRATED CIRCUITS; SIGNAL PROCESSING;

FREQUENCY MULTIPLYING CIRCUITS;

EID: 77950431072     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. P. K. Meher, "New approach to LUT implementation and accumulation for memory-based multiplication," in Proc. IEEE International Symposium on Circuits and Systems, ISCAS '09, May 2009, pp. 453-456.
2. International Technology Roadmap for Semiconductors. [Online]. Available: http://public.itrs.net/
3. H.-R. Lee, C.-W. Jen, and C.-M. Liu, "On the design automation of the memory-based VLSI architectures for FIR filters," IEEE Trans. Consumer Electronics, vol.39, no.3, pp. 619-629, Aug. 1993.
4. H.-C. Chen, J.-I. Guo, T.-S. Chang, and C.-W. Jen, "A memory-efficient realization of cyclic convolution and its application to discrete cosine transform," IEEE Trans. Circuits Syst for Video Technol., vol.15, no.3, pp. 445-453, Mar. 2005.
5. D. F. Chiper, M. N. S. Swamy, M. O. Ahmad, and T. Stouraitis, "Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST," IEEE Trans. Circuits Syst-I: Regular Papers, vol.52, no.6, pp. 1125-1137, June 2005.
6. P. K. Meher, "Systolic designs for DCT using a low-complexity concurrent convolutional formulation," IEEE Trans. Circuits & Systems for Video Technology, vol.16, no.9, pp. 1041-1050, Sept. 2006.