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Volumn , Issue , 2009, Pages 453-456

New approach to LUT implementation and accumulation for memory-based multiplication

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL CIRCUITS; COMPUTATIONAL DELAYS; DELAY PRODUCT; HIGH-PRECISION; LOOK-UP-TABLE; NEW APPROACHES;

EID: 70350164488     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2009.5117783     Document Type: Conference Paper
Times cited : (25)

References (7)
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    • International Technology Roadmap for Semiconductors. [Online]. Available: http://public.itrs.net/
  • 2
    • 0027647317 scopus 로고
    • On the design automation of the memory-based VLSI architectures for FIR filters
    • Aug
    • H.-R. Lee, C.-W. Jen, and C.-M. Liu, "On the design automation of the memory-based VLSI architectures for FIR filters," IEEE Trans. Consumer Electronics, vol. 39, no. 3, pp. 619-629, Aug. 1993.
    • (1993) IEEE Trans. Consumer Electronics , vol.39 , Issue.3 , pp. 619-629
    • Lee, H.-R.1    Jen, C.-W.2    Liu, C.-M.3
  • 3
    • 15244339187 scopus 로고    scopus 로고
    • A memory-efficient realization of cyclic convolution and its application to discrete cosine transform
    • Mar
    • H.-C. Chen, J.-I. Guo, T.-S. Chang, and C.-W. Jen, "A memory-efficient realization of cyclic convolution and its application to discrete cosine transform," IEEE Trans. Circuits Syst for Video Technol., vol. 15, no. 3, pp. 445-453, Mar. 2005.
    • (2005) IEEE Trans. Circuits Syst for Video Technol , vol.15 , Issue.3 , pp. 445-453
    • Chen, H.-C.1    Guo, J.-I.2    Chang, T.-S.3    Jen, C.-W.4
  • 4
    • 22144453965 scopus 로고    scopus 로고
    • Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST
    • June
    • D. F. Chiper, M. N. S. Swamy, M. O. Ahmad, and T. Stouraitis, "Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST," IEEE Trans. Circuits Syst-I: Regular Papers, vol. 52, no. 6, pp. 1125-1137, June 2005.
    • (2005) IEEE Trans. Circuits Syst-I: Regular Papers , vol.52 , Issue.6 , pp. 1125-1137
    • Chiper, D.F.1    Swamy, M.N.S.2    Ahmad, M.O.3    Stouraitis, T.4
  • 5
    • 33749843835 scopus 로고    scopus 로고
    • Systolic designs for DCT using a low-complexity con-current convolutional formulation
    • Sept
    • P. K. Meher, "Systolic designs for DCT using a low-complexity con-current convolutional formulation," IEEE Trans. Circuits & Systems for Video Technology, vol. 16, no. 9, pp. 1041-1050, Sept. 2006.
    • (2006) IEEE Trans. Circuits & Systems for Video Technology , vol.16 , Issue.9 , pp. 1041-1050
    • Meher, P.K.1
  • 6
  • 7
    • 70350162813 scopus 로고    scopus 로고
    • TSMC 0.l8um Process 1.8-Volt SAGE-X™ Standard Cell Library Databook, Release 4.1. Sunnyvale, CA: Artisan Components, Sept. 2003
    • TSMC 0.l8um Process 1.8-Volt SAGE-X™ Standard Cell Library Databook, Release 4.1. Sunnyvale, CA: Artisan Components, Sept. 2003.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.