A simple, verified validator for software pipelining

ACM SIGPLAN Notices

Volumn 45, Issue 1, 2010, Pages 83-92

  Tristan, Jean Baptiste ^a   Leroy, Xavier ^a  

^a INRIA   (France)

Author keywords

Software pipelining; Symbolic evaluation; Translation validation; Verified compilers

Indexed keywords

MODEL CHECKING; SEMANTICS;

INSTRUCTION LEVEL PARALLELISM; LOOP OPTIMIZATIONS; LOOP TRANSFORMATION; PERFORMANCE CHARACTERISTICS; SOFTWARE PIPELINING; SYMBOLIC EVALUATION; TRANSLATION VALIDATION;

SCHEDULING ALGORITHMS;

EID: 77149150953     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: 10.1145/1707801.1706311     Document Type: Conference Paper

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