Validating software pipelining optimizations

Proceedings of the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES '02

Volumn , Issue , 2002, Pages 280-287

  Leviathan, Raya ^a   Pnueli, Amir ^a  

^a WEIZMANN INSTITUTE OF SCIENCE   (Israel)

Author keywords

Compilers; Optimization; Pipeline processors; Translation validation; Verification

Indexed keywords

INSTRUCTION LEVEL PARALLELISM; PIPELINE PROCESSOR; PIPELINE PROCESSORS; PROOF OBLIGATIONS; SIMULATION RELATION; SOFTWARE PIPELINING; TRANSLATION VALIDATION; VERIFICATION CONDITION;

COMPUTER SOFTWARE SELECTION AND EVALUATION; EMBEDDED SYSTEMS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; SYNTHESIS (CHEMICAL); VERIFICATION;

PROGRAM COMPILERS;

EID: 33644586062     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581630.581676     Document Type: Conference Paper

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