Characterizing the resource-sharing levels in the UltraSPARC T2 processor

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 481-492

  Čakarević, Vladimir ^a   Radojković, Petar ^a   Verdú, Javier ^b   Pajuelo, Alex ^b   Cazorla, Francisco J ^a   Nemirovsky, Mario ^a   Valero, Mateo ^a,b  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

CMP; CMT; Job scheduling; Performance characterization; Simultaneous multithreading; Sun Nigara T2

Indexed keywords

CACHE HIERARCHIES; CHIP DESIGN; CHIP MULTIPROCESSOR; CMT; HARDWARE RESOURCES; INSTRUCTION LEVEL PARALLELISM; JOB SCHEDULING; LOAD-BALANCING; MULTI-LEVEL; MULTITHREADED; NETWORK APPLICATIONS; OPERATING SYSTEM DESIGN; OPERATING SYSTEMS; PROCESSOR DESIGN; PROCESSOR PERFORMANCE; RESOURCE SHARING; SIMULTANEOUS MULTI-THREADING; SUN MICROSYSTEMS; SYSTEM THROUGHPUT; THREAD-LEVEL PARALLELISM; THREE-LEVEL; ULTRASPARC;

COMPUTER OPERATING SYSTEMS; DESIGN; NANOTECHNOLOGY; PROGRAM PROCESSORS; SCHEDULING; SUN; SYSTEMS ANALYSIS;

MULTITASKING;

EID: 76749155488     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669173     Document Type: Conference Paper

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