Localizing transient faults using dynamic bayesian networks

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn , Issue , 2009, Pages 82-87

  Jha, Susmit ^a   Li, Wenchao ^a   Seshia, Sanjit A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BLACK-BOX COMPONENTS; DEEP SUB-MICRON; DEPLOYED SYSTEMS; DYNAMIC BAYESIAN NETWORK; FAULT MODEL; MOST PROBABLE EXPLANATION; MULTI CORE; ON-CHIP NETWORKS; PARTIALLY OBSERVABLE SYSTEMS; PHYSICAL EFFECTS; PROBABILISTIC APPROACHES; ROUTER DESIGN; SEMICONDUCTOR TECHNOLOGY; SPACE AND TIME; SYSTEM LEVELS; SYSTEM STATE; THIRD PARTIES; TRANSIENT ERRORS; TRANSIENT FAULTS;

DESIGN; DISTRIBUTED PARAMETER NETWORKS; ERRORS; INFERENCE ENGINES; INTELLIGENT NETWORKS; SEMICONDUCTOR DEVICE MANUFACTURE; SPEECH RECOGNITION;

BAYESIAN NETWORKS;

EID: 76649121202     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2009.5340170     Document Type: Conference Paper

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