Test access mechanism for multiple identical cores

Proceedings - International Test Conference

Volumn , Issue , 2009, Pages

  Giles, Grady ^a   Wang, Jing ^a   Sehgal, Anuja ^a   Balakrishnan, Kedamath J ^a   Wingfield, James ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED CORES; HIGH-VOLUME PRODUCTION; LOW-YIELD; TEST ACCESS MECHANISM; TEST TIME;

TESTING;

EID: 76549128525     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2009.5355560     Document Type: Conference Paper

References (12)

1. Parulkar I., et. al., "A Scalable, Low Cost Design-fortest architecture for UltraSPARC Chip Multi-Processors", Proc. of International Test Conference, pp. 726-735, 2002.
2. Riley, M., et. al., "Testability Features of the First-Generation Cell Processor", Proc. of International Test Conference, Paper 6.1, 2005.
3. Tan, P. J., et. al., "Testing of the UltraSPARC Tl Microprocessor and Its Challenges", Proc. of International Test Conference, Paper 16.1,2006.
4. Molyneaux, R., et. al., "Design for Testability Features of the SUN Microsystems Niagara2 CMP-CMT SPARC Chip", Proc. of International Test Conference, Paper 1.2, 2007.
5. Silva, F. D., et. al., The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500™, Springer-Verlag New York, LLC, 2006.
6. Zorian, Y., et. al., "Testing Embedded-Core Based System Chips", Proc. Of International Test Conference, Paper 6.2, 1998.
7. Goel, S. K., et. al., "Effective and Efficient Test Architecture Design for SOCs", Proc. OfInternational Test Conference, Paper 19.2, 2002.
8. Makar S., et. al., "Testing of Vega2, a Chip MultiProcessor with Spare Processors", Proc. of International Test Conference, Paper 9.1,2007.
9. Atwell W. D. Jr., et. al., "Tester on a Chip (TOAC) or Appratus for Application of Tests for Embedded Test Points", Journal of Motorola Technical Developments, Volume 9, 1989.
10. Wood, T., et. al., "The Test Features of the Quad-Core AMD Opteron™ Microprocessor", Proc. of International Test Conference, 2008
11. Stapper C. H., et. al., "Yield Model for ASIC and Processor Chips", International Workshop on Defect and Fault Tolerance in VLSI System, 1993.
12. Marinissen E. J., et. al., "The Role of Test Protocols in Testing Embedded-Core-Based System ICs", European Test Workshop, 1999.