A 5Mgate/414mW networked media SoC in 0.13um CMOS with 72p multi-standard video decoding

Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Volumn , Issue , 2009, Pages 385-388

  Ning, Ma ^a   Pang, Zhibo ^a   Chen, Jun ^a   Tenhunen, Hannu ^a   Zheng, Li Rong ^a,b  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b FUDAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; CLOCK GATING; CMOS TECHNOLOGY; COARSE-GRAINED; CONFIGURABLE; DIE SIZE; DYNAMIC CONFIGURATION; ETHERNET INTERFACE; LOW-POWER DESIGN; MAXIMUM POWER; MULTI-STANDARD; NETWORKED MEDIA; POWER CONSUMPTION; POWER MANAGEMENT STRATEGIES; RISC CORE; SINGLE-POLY; SUPPLY VOLTAGES; SYSTEM FREQUENCY; VIDEO DECODING; VIDEO STREAMS; VIDEO-STREAM DECODING;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY MANAGEMENT; ETHERNET; MICROPROCESSOR CHIPS; MOTION PICTURE EXPERTS GROUP STANDARDS; PROGRAMMABLE LOGIC CONTROLLERS; VIDEO STREAMING;

DECODING;

EID: 76249116270     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2009.5357177     Document Type: Conference Paper

References (10)

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