Heterogeneous multicore SoC for secure multimedia applications

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 675-678

  Kondo, Hiroyuki ^a   Nakajima, Masami ^a   Otani, Sugako ^a   Yamamoto, Osamu ^a   Masui, Norio ^a   Okumura, Naoto ^a   Sakugawa, Mamoru ^a   Kitao, Masaya ^a   Ishimi, Koichi ^a   Sato, Masayuki ^a   Fukuzawa, Fumitaka ^a   Inaoka, Kazuhiro ^b   Saito, Yoshihiro ^b   Arimoto, Kazutami ^a   Shimizu, Toru ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Solutions Corporation   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS; CMOS INTEGRATED CIRCUITS; CONCURRENCY CONTROL; COPYRIGHTS; CRYPTOGRAPHY; DATA STORAGE EQUIPMENT; DATA VISUALIZATION; DECODING; INTEGRATED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS;

CMOS TECHNOLOGIES; CONFIDENTIAL INFORMATIONS; DDR MEMORIES; DIGITAL CONTENTS; DIGITAL RIGHTS MANAGEMENTS; HARDWARE AND SOFTWARES; HETEROGENEOUS MULTICORE; HIGH RESOLUTIONS; LOW POWERS; MATRIX PROCESSORS; MEMORY MANAGEMENTS; MULTIMEDIA APPLICATIONS; MULTIMEDIA PROCESSORS; SECURE DATUMS; SENSITIVE INFORMATIONS; SOFTWARE SYSTEMS; VIDEO PROCESSING APPLICATIONS;

MULTIMEDIA SYSTEMS;

EID: 57849084418     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672175     Document Type: Conference Paper

References (4)

1. S. Kaneko et al., "A 600MHz Single-Chip Multiprocessor with 4.8GB/s Internal Shared Pipelined Bus and 512kB Internal Memory", IEEE Journal of Solid-State Circuits, Vol. 39,No.1, pp. 184-193, January 2004
2. H. Noda et al., "The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture", IEEE Journal of Solid-State Circuits Vol.42, No.1, pp. 183-192, January 2007.
3. M. Nakajima et al., "Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors", VLSI Symposium on Circuits, Dig. Tech. Papers, Paper 2.2, pp.14-15, June 2007.
4. H. Kondo et al., "Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors", IEEE Journal of Solid-State Circuits Vol.43, No.4, pp.892-901, April 2008