A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance

Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Volumn , Issue , 2009, Pages 157-160

  Huang, Guan Ying ^a   Liu, Chun Cheng ^a   Lin, Ying Zu ^a   Chang, Soon Jyh ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; BIT RESOLUTION; CMOS PROCESSS; INPUT CAPACITANCE; SUCCESSIVE APPROXIMATIONS; SUCCESSIVE-APPROXIMATION ADC;

APPROXIMATION THEORY; CAPACITANCE; CMOS INTEGRATED CIRCUITS;

MULTICARRIER MODULATION;

EID: 76249108648     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2009.5357202     Document Type: Conference Paper

References (6)

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3. H. C. Hong and G. M. Lee, A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC, IEEE J. Solid-State Circuits, vol.42, pp. 2161-2167, OCT. 2007.
4. C. C. Liu, S. J. Chang, G. Y. Huang and. Y. Z. Lin, A 0.92m.W 10-bit 50-M:S/S SAR ADC in 0.13μm CMOS process, IEEE Symp. on VLSI Circuits, Jun. 2009, pp. 236-237.
5. J. Graninckx and G. Van der Plas, A 650/conversion-step 0-to- 50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS, IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 246-247.
6. A. M. Abo, P. R. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipelined, analog-to-digital converter, IEEE J. Solid State Circuits, vol.34, no.5, pp. 599-606, May 1999.