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Volumn 19, Issue 1, 2009, Pages 155-164

Opportunities and challenges for germanium and silicon-germanium channel p-FETs

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ENERGY GAP; GATE DIELECTRICS; GERMANIUM; HIGH TEMPERATURE ENGINEERING; HIGH-K DIELECTRIC; LOGIC GATES; SILICON; THRESHOLD VOLTAGE;

EID: 74949138752     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3118941     Document Type: Conference Paper
Times cited : (9)

References (11)
  • 6
    • 64549151191 scopus 로고    scopus 로고
    • B, Frank
    • B. (Frank) Yang et al., IEDM Tech. Dig., 2007, p. 1032.
    • (2007) IEDM Tech. Dig , pp. 1032
    • Yang1
  • 11
    • 74949134518 scopus 로고    scopus 로고
    • S-H. Lee, P. Majhi, J. Oh, W-Y. Loh, B. Sassman, B-K. Min, P. Y. Hung, S. McCoy, J. Chen, D. Heh, C. Young, J. Huang, P. Patel, S. Suthram, P. D. Kirsch, H. R Harris, H-H. Tseng, W. Tsai, S. Datta, S. K. Banerjee and R. Jammy, IEDM Tech. Dig., 2008.
    • S-H. Lee, P. Majhi, J. Oh, W-Y. Loh, B. Sassman, B-K. Min, P. Y. Hung, S. McCoy, J. Chen, D. Heh, C. Young, J. Huang, P. Patel, S. Suthram, P. D. Kirsch, H. R Harris, H-H. Tseng, W. Tsai, S. Datta, S. K. Banerjee and R. Jammy, IEDM Tech. Dig., 2008.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.