A novel trace-pipelined binary arithmetic coder architecture for JPEG2000

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2009, Pages 244-248

  Rhu, Minsoo ^a   Park, In Cheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Arithmetic coding; EBCOT; JPEG2000; Trace scheduling; VLSI architecture

Indexed keywords

DECODING; PIPELINES; SILICON COMPOUNDS;

ARITHMETIC CODING; BINARY ARITHMETIC CODERS; CRITICAL PATH DELAYS; EBCOT; EMBEDDED BLOCK CODING WITH OPTIMIZED TRUNCATION; JPEG 2000; PROPOSED ARCHITECTURES; VLSI ARCHITECTURES;

SIGNAL PROCESSING;

EID: 74549197635     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2009.5336259     Document Type: Conference Paper

References (10)

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