High-speed implementation of JBIG arithmetic coder

IEEE Region 10 Annual International Conference, Proceedings/TENCON

Volumn 2, Issue , 1999, Pages 1291-1294

  Tarui, M ^a   Oshita, M ^b   Onoye, T ^a   Shirakawa, I ^a  

^a OSAKA UNIVERSITY   (Japan)

^b Mita Industrial Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPYING;

ARITHMETIC CODERS; CRITICAL PATH DELAYS; DIGITAL COPYING; HIGH SPEED IMPLEMENTATION; HIGH-SPEED ARCHITECTURES; PIPELINED ARCHITECTURE; PROBABILITY ESTIMATION; PROPOSED ARCHITECTURES;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 85013905978     PISSN: 21593442     EISSN: 21593450     Source Type: Conference Proceeding    
DOI: 10.1109/TENCON.1999.818665     Document Type: Conference Paper

References (2)

1. I S W I nternatid SMdd 11544:lTU-T RE T. 82, coded Repressetalion of Pidue and Audio Information-progresSe Bi-level Image Compression, 1993.
2. ITU-T Rec T. 85, Application pmfile for Recommendation T. 82-progressive bi-level image compression (JBIG coding scheme) for himile apparatus