A three-level parallel high-speed low-power architecture for EBCOT of JPEG 2000

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 16, Issue 9, 2006, Pages 1153-1163

  Li, Yijun ^a,b   Bayoumi, Magdy ^a,b  

^a IEEE   (United States)

^b University of Louisiana at Lafayette   (United States)

Author keywords

EBCOT tier 1; High speed; JPEG 2000; Low power; Memory efficient; VLSI architecture

Indexed keywords

EBCOT TIER-1; JPEG 2000; MEMORY-EFFICIENT; VLSI ARCHITECTURE;

BIT ERROR RATE; COMPUTER HARDWARE; IMAGE CODING; OPTIMIZATION; SWITCHING;

MULTIMEDIA SYSTEMS;

EID: 33749859303     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2006.881864     Document Type: Article

References (25)

1. M. Boliek, C. Christopoulos, and E. Majani, JPEG2000 Part I: Final Publication Draft, ISO/IEC JTC1/SC29/WG1 N2678, Jul. 2002.
2. C.-J. Lian, K.-F. Chen, H.-H. Chen, and L.-G. Chen, "Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000," IEEE Trans. Circuits. Syst. Video Technol., vol. 13, no. 3, pp. 219-230, Mar. 2003.
3. Y. Li, R. E. Aly, B. Wilso, and M. A. Bayoumi, "Analysis and enhancement for EBCOT in high speed JPEG2000 architectures," in Proc. 45th Midwest Symp. Circuits Syst., 2002, vol. 2, pp. 736-739.
4. J.-S. Chiang, Y.-S. Lin, and C.-Y. Hsieh, "Efficient pass-parallel architecture for EBCOT in JPEG2000," in Proc. IEEE Int. Symp. Circuits Syst., May 2002, vol. 1, pp. 773-776.
5. H.-C. Fang, T.-C. Wang, C.-J. Lian, T.-H. Chang, and L.-G. Chen, "High speed memory efficient EBCOT architecture for JPEG2000," in IEEE Int. Symp. Circuits Syst. (ISCAS 2003), May 2003, vol. 2, pp. 736-739.
6. K. Andra, T. Acharya, and C. Chakrabarti, "Efficient VLSI implementation of bit plane coder of JPEG2000," in Proc. SPIE Int. Conf. Applicat. Digit. Image Process. XXIV, Jul. 2001, vol. 4472, pp. 246-257.
7. Y. Li, R. E. Aly, M. A. Bayoumi, and S. A. Mashali, "Parallel highspeed architecture for EBCOT in JPEG2000," in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., Apr. 2003, vol. 2, pp. 481-484.
8. Y. Li and M. Bayoumi, "Three-level parallel high speed architecture for ebcot in JPEG 2000," in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., Mar. 2005, vol. 5, pp. 5-8.
9. K.-K. Ong, W.-H. Chang, Y.-C. Tseng, Y.-S. Lee, and C.-Y. Lee, "A high throughput low cost context-based adaptive arithmetic codec for multiple standards," in Proc. IEEE Int. Conf, Image Process., Sep. 2002, vol. 1, pp. 872-875.
10. J.-S. Chiang, C.-H. Chang, Y.-S. Lin, C.-Y. Hsieh, and C.-H. Hsia, "High-speed EBCOT with dual context-modeling coding architecture for JPEG2000,"in Proc. IEEE Int. Symp. Circuits Syst., May 2004, vol. 3, pp. 865-868.
11. H. H. Chen, C. J. Lian, K. F. Chen, and L. G. Chen, "Context-based adaptive arithmetic encoder design for jpeg2000," presented at the Taiwan VLSI Design/CAD Symp. 2001, Aug. 2001, C1-10.
12. M. Tarui, M. Oshita, T. Onoye, and I. Shirakawa, "High-speed implementation of JBIG arithmetic coder," in Proc. TENCON'99, 1999, vol. 2, pp. 1291-1294.
13. Y. Li, M. Elgamel, and M. Bayoumi, "A partial parallel algorithm and architecture for arithmetic encoder in JPEG 2000," in Proc. IEEE Int. Symp. Circuits Syst., May 2005, pp. 5198-5201.
14. JPEG2K E, , Oct. 2002 [Online], Available: http://www.alma-tech.com/
15. CS6510, , Oct. 2002 [Online]. Available: http://www.amphion.com/cs6510. html
16. K. Andra, C. Chakrabarti, and T. Acharya, "A high-performance JPEG 2000 architecture," IEEE Trans. Circuits. Syst. Video Technol., vol. 13, no. 3, pp. 209-218, Mar. 2003.
17. ADV202. , Oct. 2002 [Online], Available: http://www.analog.com/
18. H. Yamauchi, S. Okada, K. Taketa, T. Ohyama, Y. Matsuda, T. Mori, S. Okada, T. Watanabe, Y. Matsuo, Y. Yamada, T. Ichikawa, and Y. Matsushita, "Image processor capable of block-noise-free JPEG 2000 compression with 30 frames/s for digital camera applications," in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 46-47.
19. H. Yamauchi, K. Mochizuki, K. Taketa, T. Watanabe, T. Mon, Y. Matsuda, Y. Matsushita, A. Kabayashi, and S. Okada, "A 1440 × 1080 pixels 30 frames/s motion-JPEG2000 codec for HD movie transmission," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 326-327.
20. H.-C. Fang, C.-T. Huang, Y.-W. Chang, T.-C. Wang, P.-C. Tseng, C.-J. Lian, and L.-G. Chen, "81 ms/s JPEG 2000 single chip encoder with rate-distoration optimization," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 328-329.
21. H.-C. Fang, Y.-W. Chang, C.-C. Cheng, C.-C. Chen, and L.-G. Chen, "Memory efficient JPEG 2000 architecture with stripe pipeline scheme," in Proc. IEEE Int. Conf. Accoust., Speech, Signal Process., Mar-. 2005, vol. 5, pp. 1-4.
22. K. Andra, C. Chakrabarti, and T. Acharya, "A VLSI architecture for lifting-based forward and inverse wavelet transform," IEEE Trans. Signal Process., vol. 50, no. 4, pp. 966-977, Apr. 2002.
23. B.-F. Wu and C.-F. Lin, "Analysis and architecture design for high performance JPEG 2000 coprocessor," in Proc. IEEE Int. Symp. Circuits Syst., May 2004, vol. 2, pp. 225-228.
24. K. Andra, C. Chakrabarti, and T. Acharya, "A high-performance JPEG2000 architecture," IEEE Trans. Circuits. Syst. Video Technol., vol. 13, no. 2, pp. 209-218, Mar. 2002.
25. M. D. Adams, JasPer Software Reference Manual (Version 1.700.0), ISO/IEC JTC1/SC29/WG1 N2415, Feb. 2003.