Massively parallel implementation of cyclic LDPC codes on a general purpose graphics processing unit

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2009, Pages 285-290

  Ji, Hyunwoo ^a   Cho, Junho ^a   Sung, Wonyong ^a  

^a Seoul National University   (South Korea)

Author keywords

Compute unified device architecture (CUDA); General purpose graphics processing unit (GPGPU); Low density parity check (LDPC) codes; Parallel processing

Indexed keywords

COMPUTE UNIFIED DEVICE ARCHITECTURES; GENERAL PURPOSE; GRAPHICS PROCESSING UNIT; LOW-DENSITY PARITY-CHECK CODES; PARALLEL PROCESSING;

DECODING; IMAGE CODING; MATRIX ALGEBRA; SIGNAL PROCESSING;

PROGRAM PROCESSORS;

EID: 74549124820     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2009.5336268     Document Type: Conference Paper

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