Event-driven configuration of a neural network CMP system over a homogeneous interconnect fabric

8th International Symposium on Parallel and Distributed Computing, ISPDC 2009

Volumn , Issue , 2009, Pages 54-61

  Khan, M M ^a   Navaridas, J ^b   Rast, A D ^a   Jin, X ^a   Plana, L A ^a   Lujan M ^a   Woods, J V ^a   Miguel Alonso, J ^b   Furber, S B ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

^b UNIVERSITY OF THE BASQUE COUNTRY UPV EHU   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS COMMUNICATION; CHIP MULTIPROCESSORS; CONFIGURATION PROCESS; EVENT DRIVEN; FULL-SCALE SYSTEM; HARDWARE SUPPORTS; HIGH-SPEED; HOMOGENEOUS NETWORK; INTER PROCESSOR COMMUNICATION; INTERCONNECT FABRICS; LOADING TIME; LOCAL CONTROL; OPERATING CONDITION; PARALLEL SYSTEM; RUN TIME RECONFIGURATION; RUNTIMES; STATE INFORMATION; SYNCHRONISATION; SYSTEM CONTROL; SYSTEMC; TRANSITION SEQUENCES; TWO STAGE; USER-SYSTEM INTERACTION; VERILOG SIMULATION;

COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DISTRIBUTED COMPUTER SYSTEMS; FAULT TOLERANCE; LOADING; NANOTECHNOLOGY; NEURAL NETWORKS; QUALITY ASSURANCE;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 74349113994     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPDC.2009.25     Document Type: Conference Paper

References (14)

1. P. Dayan and L.F. Abbott. "Theoretical Neuroscience". MIT Press, Cambridge, 2001.
2. S.B. Furber, S. Temple, and A.D. Brown. "High-Performance Computing for Systems of Spiking Neurons". In AISB'06 workshop on GC5: Architecture of Brain and Mind, volume 2, pages 29-36, Bristol, April 2006.
3. F. Ghenassia. "Transaction-Level Modeling with Systemc: TLM Concepts and Applications for Embedded Systems". Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2006.
4. R. A. Haring and R. Bellofatto et al. "Blue Gene/L Compute Chip: Control, Test and Bring up Intrastructure". IBM Journal of Research and Development, 49(2/3):289-301, 2005.
5. Cray Inc. "Cray XT3 Datasheet". Cray Inc., Jan. 2005.
6. E.M. Izhikevich, J.A. Gally, and G.M. Edelman. "Spike-Timing Dynamics of Neuronal Groups". Cerebral Cortex, 14(8):933-944, 2004.
7. A. Jahnke, T. Scḧonauer, U. Roth, K. Mohraz, and H. Klar. "Simulation of Spiking Neural Networks on Different Hardware Platforms". In Proc. 1997 Int'l Conf. Artificial Neural Networks (ICANN 1997), pages 1187-1192, 1997.
8. X. Jin, S.B. Furber, and J.V. Woods. "Efficient Modelling of Spiking Neural Networks on a Scalable Chip Multiprocessor". In Proc. 2008 Int'l Joint Conf. on Neural Networks (IJCNN2008), 2008.
9. M. Khan, X. Jin, S. Furber, and L.A. Plana. "System-Level Model for a GALS Massively Parallel Multiprocessor". In Proc. 19th UK Asynchronous Forum, pages 9-12, London, September 2007.
10. M.M. Khan, D.R. Lester, L.A. Plana, A. Rast, X. Jin, E. Painkras, and S.B. Furber. "SpiNNaker: Mapping Neural Networks onto a Massively-Parallel Chip Multiprocessor". In Proc. 2008 Int'l Joint Conf. on Neural Networks (IJCNN2008), 2008.
11. H. Kopetz. "Real-Time Systems: Design Principles for Distributed Embedded Applications". Kluwer Academic Publishers, 1997.
12. W. Maass and C. M. Bishop (ed). "Pulsed Neural Networks". MIT Press, Cambridge, Massachusetts, 1998.
13. A.D. Rast, S. Yang, M. Khan, and S.B. Furber. "Virtual Synaptic Interconnect Using an Asynchronous Network-on-Chip". In Proc. 2008 Int'l Joint Conf. on Neural Networks (IJCNN2008), 2008.
14. T. P. Trappenberg. "Fundamentals of Computational Neuroscience". Oxford University Press, New York, 2002.