-
2
-
-
0024931558
-
Feature linking via stimulus-evoked oscillations: Experimental results from cat visual cortex and functional implication from a network model
-
R. Eckhorn, H. J. Reitboeck, M. Arndt, P. Dicke, “Feature linking via stimulus-evoked oscillations: Experimental results from cat visual cortex and functional implication from a network model”, Proc. ICNNI: 723-730,1989.
-
(1989)
Proc. ICNNI
, pp. 723-730
-
-
Eckhorn, R.1
Reitboeck, H.J.2
Arndt, M.3
Dicke, P.4
-
3
-
-
0024541876
-
Stimulus-specific neuronal oscillations in orientation columns of cat visual cortex
-
C. M. Gray, W. Singer, “Stimulus-specific neuronal oscillations in orientation columns of cat visual cortex”, Proc. Natl. Acad. Sei. USA 86: 1698-1702,1989
-
(1989)
Proc. Natl. Acad. Sei. USA
, vol.86
, pp. 1698-1702
-
-
Gray, C.M.1
Singer, W.2
-
5
-
-
0000373485
-
Towards a neurobiological theory of consciousness
-
F. Crick and C. Koch, “Towards a neurobiological theory of consciousness”, Seminars in The Neuroscience 2: 263-275, 1990.
-
(1990)
Seminars in the Neuroscience
, vol.2
, pp. 263-275
-
-
Crick, F.1
Koch, C.2
-
6
-
-
0027357806
-
A biologically motivated and analytically soluble model of collective oscillations in the cortex
-
W. Gerstner, R. Ritz, J. L. van Hemmen, “A biologically motivated and analytically soluble model of collective oscillations in the cortex”, Biol. Cybern. 68: 363-374,1993.
-
(1993)
Biol. Cybern
, vol.68
, pp. 363-374
-
-
Gerstner, W.1
Ritz, R.2
Van Hemmen, J.L.3
-
7
-
-
0001781836
-
Lower Bounds for the Computational Power of Networks of Spiking Networks
-
W. Maass, “Lower Bounds for the Computational Power of Networks of Spiking Networks”, Neural Computations (1), 1-40, 1996.
-
(1996)
Neural Computations
, Issue.1
, pp. 1-40
-
-
Maass, W.1
-
8
-
-
84947458844
-
Silicon Auditory Processors as Computer Peripherals
-
J. Lazarro, J. Wawrzynek, “Silicon Auditory Processors as Computer Peripherals”, NIPS 5: 820-827,1993.
-
(1993)
NIPS
, vol.5
, pp. 820-827
-
-
Lazarro, J.1
Wawrzynek, J.2
-
9
-
-
0029531761
-
An Artificial Neural Network Accelerator for Puls-Coded Model-Neurons
-
Perth, Australia
-
G. Frank, G. Hartmann, “An Artificial Neural Network Accelerator for Puls-Coded Model-Neurons”, ICNN’95, Perth, Australia, 1995
-
(1995)
ICNN’95
-
-
Frank, G.1
Hartmann, G.2
-
10
-
-
2042497344
-
Towards Efficient Hardware for Spike-Processing Neural Networks
-
A. Jahnke, U. Roth, H. Klar, “Towards Efficient Hardware for Spike-Processing Neural Networks”, Proc. World Congress on Neural Networks, 460-463,1995.
-
(1995)
Proc. World Congress on Neural Networks
, pp. 460-463
-
-
Jahnke, A.1
Roth, U.2
Klar, H.3
-
11
-
-
84947445436
-
Hardware Requirements for Spike-Processing Neural Networks
-
U. Roth, A. Jahnke, H. Klar, “Hardware Requirements for Spike-Processing Neural Networks”, Proc. IWANN’95,720-727,1995.
-
(1995)
Proc. IWANN’95
, pp. 720-727
-
-
Roth, U.1
Jahnke, A.2
Klar, H.3
-
12
-
-
84943258542
-
Object Separation in Dynamic Neural Networks
-
H.J. Reitböck, M. Stöcker, C. Hahn, “Object Separation in Dynamic Neural Networks”, Proc. ICNN, II: 638-641,1993.
-
(1993)
Proc. ICNN, II
, pp. 638-641
-
-
Reitböck, H.J.1
Stöcker, M.2
Hahn, C.3
-
13
-
-
0025532312
-
A VLSI Architecture for High-Performance, Low-Cost, On-Chip Learning
-
D. Hammerstrom, “A VLSI Architecture for High-Performance, Low-Cost, On-Chip Learning,” Proc. IJCNN, 537-543,1990.
-
(1990)
Proc. IJCNN
, pp. 537-543
-
-
Hammerstrom, D.1
-
14
-
-
0026382865
-
Architecture of a General Purpose Neural Signal Processor
-
Ramacher U, Beichter J, Briils N, “Architecture of a General Purpose Neural Signal Processor”, Proc IJCNN I: 443-446,1991
-
(1991)
Proc IJCNN I
, pp. 443-446
-
-
Ramacher, U.1
Beichter, J.2
Briils, N.3
-
16
-
-
0000756387
-
Efficient Simulation of Biological Neural Networks on Massively Parallel Supercomputers with Hypercube Architecture
-
E. Niebur, D. Brettle, “Efficient Simulation of Biological Neural Networks on Massively Parallel Supercomputers with Hypercube Architecture”, NIPS 6: 904-910,1993.
-
(1993)
NIPS
, vol.6
, pp. 904-910
-
-
Niebur, E.1
Brettle, D.2
-
17
-
-
0013222481
-
A SIMD/Dataflow Architecture for a Neurocomputer for Spike-Processing Neural Networks (NESPINN)
-
A. Jahnke, U. Roth, H. Klar: “A SIMD/Dataflow Architecture for a Neurocomputer for Spike-Processing Neural Networks (NESPINN)”, MicroNeuro’96, 232-237,1996.
-
(1996)
MicroNeuro’96
, pp. 232-237
-
-
Jahnke, A.1
Roth, U.2
Klar, H.3
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