Controlling energy and process variability in System-on-Chips: Needs for control theory

Proceedings of the IEEE International Conference on Control Applications

Volumn , Issue , 2009, Pages 302-307

  Fesquet, Laurent ^a   Zakaria, Hatem ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; CLOCK GENERATOR; CLOCK PERIOD; COMPLEX NETWORKS; CONTROL LAWS; CONTROL TECHNIQUES; CRITICAL PATHS; ENVIRONMENTAL PARAMETER; FABRICATION PROCESS; FABRICATION YIELD; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; MULTIPLE CLOCK DOMAINS; NONUNIFORM; PROCESS VARIABILITY; SPECIFIC POWER; SPECIFIC SENSORS; SYNCHRONISATION; SYSTEM ON CHIPS; TIMING CONSTRAINTS;

ASYNCHRONOUS GENERATORS; CLOCKS; CONTROL THEORY; ELECTRIC NETWORK TOPOLOGY; MICROPROCESSOR CHIPS; SENSORS; SYNCHRONOUS GENERATORS; TIMING CIRCUITS; TIMING JITTER;

PROCESS CONTROL;

EID: 74049157019     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCA.2009.5280864     Document Type: Conference Paper

References (19)

1. M. Pedram, "Design Technologies for Low Power VLSI", in Encyclopedia of Computer Science and Technology, vol. 36, Marcel Dekker, Inc., 1997, pp. 73-96.
2. L. Benini, A. Bogliolo, and G. De Micheli, "A Survey of Design Techniques for System-Level Dynamic Power Management", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, No 3, June 2000, pp. 299-316.
3. L. Kelly, and C. Piguet, "Low-power Electronics Design", CRC Press, 2005, ISBN 0-8493-1941-2.
4. T. Simunic, L. Benini., A. Acquaviva, G. De Micheli, "Dynamic Voltage Scaling for Portable Systems", 38th Design Automation Conference, Las Vegas, 18-22 June 2001, pp. 524-529.
5. Y.H. Lu, and G. De Micheli "Comparing System-Level Power Management Policies", IEEE Design & test of Computers, 2001, pp. 10-19.
6. D. Rios-Arambula, A. Buhrig, G. Sicard, M. Renaudin, "On the use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits", Journal on Low Power Electronics vol. 2, pp 45-55, April 2006
7. K. Flautner, D. Flynn, D. Roberts, and D. Patel, "An Energy Efficient SoC with Dynamic Voltage Scaling", DATE, IEEE, February 2004, Vol. 3, pp. 324 - 327.
8. A. Varma, B. Ganesh, and M. Sen, "A Control-Theoretic Approach to Dynamic Voltage Scheduling", CASES, October - November 1, 2003, San Jose CA, USA.
9. Y. Zhu and F. Mueller, "Feedback Dynamic Voltage Scaling DVS-EDF Scheduling: Correctness and PID-Feedback", North Carolina State University, 2003, TR-2003-13.
10. F.R. Boyer, H.G. Epassa and Y. Savaria, "Embedded power-aware cycle by cycle variable speed processor", Computers and Digital Techniques, IEE Proceedings - 3 July 2006, Vol. 153, Issue 4, pp. 283 - 290.
11. M. Stork, "Digital building block for frequency synthesizer and fractional phase locked loops", SympoTIC, IEEE, October 2003, pp. 126 - 129.
12. S. Fairbanks and S. Moore, "Analog micropipeline rings for high precision timing", ASYNC'04, CRETE, Greece, IEEE, April 2004, pp. 41-50.
13. J. Hamon, L. Fesquet, B. Miscopein and M. Renaudin "High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators", ASYNC'08, Newcastle, UK, IEEE, April 2008, pp. 29-38.
14. R. Mullins and S. Moore, "Demystifying Data-Driven and Pausible Clocking Schemes", ASYNC'07, Berkeley, California, USA, IEEE, March 2007, pp. 175-185.
15. J. P. Josep Rius, and M. Meijer, "An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits", PATMOS, 2005, 3728, 187-196.
16. th International Symposium on High-Performance Computer Architecture, page 29, Washington, DC, USA, 2002, IEEE Computer Society.
17. G. Magklis et al., "Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor", Micro-IEEE, Vol. 23, November-December 2003, pp. 62-68.
18. H. Zakaria et al., "Integrated Asynchronous Regulation for Nanometric Technologies: Application to an Embedded Parallel System", MINATEC CROSSROADS, 2008.
19. M. Krstic., E. Grass., F.K. Gurkaynak, P. Vivet, "Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook", IEEE Design & Test of Computers, Vol. 24, Issue 5, September-October 2007, pp. 430 - 441.