Explorations of honeycomb topologies for network-on-chip

NPC 2009 - 6th International Conference on Network and Parallel Computing

Volumn , Issue , 2009, Pages 73-79

  Yin, Alexander Wei ^a   Xu, Thomas Canhao ^a   Liljeberg, Pasi ^a   Tenhunen, Hannu ^a  

^a UNIVERSITY OF TURKU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

DEADLOCK-FREE ROUTING; DESIGN ALTERNATIVES; HONEYCOMB MESHES; IMPLEMENTATION COST; IN-NETWORK; LOGICAL NETWORK; NETWORK COSTS; NETWORK ON CHIP; RECTANGULAR MESH; TOPOLOGICAL PROPERTIES; TURN MODEL;

ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; NETWORK PERFORMANCE; PARALLEL ARCHITECTURES; THREE DIMENSIONAL;

HONEYCOMB STRUCTURES;

EID: 73449140111     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NPC.2009.34     Document Type: Conference Paper

References (13)

1. K. Efe, "A variation on the hypercube with lower diameter," IEEE Transaction of Computers, vol. 40, no. 11, pp. 1312 - 1316, Nov. 1991.
2. W. J. Dally and B. Towles, Eds., Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers, 2004.
3. X. Dong and Y. Xie, "System-level cost analysis and design exploration for three-dimensional integrated circuits (3d ics)," in Proc. Asia and South Pacific Design Automation Conference ASP-DAC 2009, 19 - 22 Jan. 2009, pp. 234 - 241.
4. A. W. Topol and et al., "Three-dimensional integrated circuits," in IBM Journal of Research and Development, November 2006.
5. B. S. Feero and P. P. Pande, "Networks-on-chip in a three-dimensional environment: A performance evaluation," IEEE Transaction on Computers, vol. 58, no. 1, pp. 32 - 45, Jan. 2009.
6. I. Stojmenovic, "Honeycomb networks: Topological properties and communication algorithms," IEEE Transaction on Parallel and Distributed Systems, vol. 8, no. 10, pp. 1036 - 1042, Oct. 1997.
7. C. Glass and L. Ni, "The turn model for adaptive routing," in Proc. 19th Annual International Symposium on Computer Architecture, May 19 - 21, 1992, pp. 278 - 287.
8. Z. Lu and A. Jantsch, "Slot allocation using logical networks for tdm virtual-circuit configuration for network-on-chip," in Proc. IEEE/ACM International Conference on Computer-Aided Design ICCAD 2007, 4 - 8 Nov. 2007, pp. 18 - 25.
9. A. W. Yin, Generalization of slot table size for virtual circuits on Nostrum networks on chip. Master Thesis in Royal Institute of Technology (KTH), Sweden, June 2008.
10. C. Decayeux and D. Seme, "3d hexagonal network: modeling, topological properties, addressing scheme, and optimal routing algorithm," IEEE Transaction on Parallel and Distributed System, vol. 16, no. 9, pp. 875 - 884, 2005.
11. F. Garcia, J. Solano, I. Stojmenovic, and M. Stojmenovic, "Higher dimensional hexagonal networks," Journal of Parallel and Distributed Computing, vol. 63, pp. 1164 - 1172, 2003.
12. P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Transaction on Computers, vol. 54, no. 8, pp. 1025 - 1040, Aug. 2005.
13. J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, M. Yousif, and C. Das, "A novel dimensionally-decomposed router for on-chip communication in 3d architectures," in Proceedings of ISCA-2007, June 2007.