A 1.2 V 12 b 60 MS/s CMOS analog front-end for image signal processing applications

ETRI Journal

Volumn 31, Issue 6, 2009, Pages 717-724

  Jeon, Young Deuk ^a   Cho, Young Kyun ^a   Nam, Jae Won ^a   Lee, Seung Chul ^a   Kwon, Jong Kee ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

ADC; AFE; Flexibility; Low power; Low voltage; Op amp preset technique; Power management technique; Programmable capacitor array scheme; VGA

Indexed keywords

CAPACITOR ARRAYS; CMOS ANALOG; CMOS PROCESSS; DIGITAL CAMCORDER; FLEXIBLE DESIGNS; GAIN ERRORS; IMAGE SIGNAL PROCESSING; LOW POWER; NON-LINEARITY; OPERATION FLEXIBILITY; PIPELINED ANALOG-TO-DIGITAL CONVERTER; POWER CONSUMPTION; POWER MANAGEMENT TECHNIQUES; SAMPLING FREQUENCIES; SMALL AREA; VARIABLE GAIN AMPLIFIERS; VARIABLE RESOLUTION;

BANDPASS AMPLIFIERS; CAPACITANCE; CAPACITORS; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER MEASUREMENT; ENERGY MANAGEMENT; INDUSTRIAL MANAGEMENT; MULTICARRIER MODULATION; SIGNAL PROCESSING; SIGNAL TO NOISE RATIO; VIDEO AMPLIFIERS; VOLTAGE REGULATORS;

DIFFERENTIAL AMPLIFIERS;

EID: 73449119597     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.09.1209.0025     Document Type: Article

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