Multi-bit sigma-delta modulator for low distortion and high-speed operation

ETRI Journal

Volumn 29, Issue 6, 2007, Pages 835-837

  Kim, Yi Gyeong ^a   Kwon, Jong Kee ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Feed forward topology; Low distortion; Low voltage; Multi bit sigma delta modulator

Indexed keywords

CMOS INTEGRATED CIRCUITS; FEEDBACK; FORMAL LOGIC; HIGH SPEED NETWORKS; SIGNAL DISTORTION;

FEEDBACK PATH; SIGNAL COMPONENTS;

DELTA SIGMA MODULATION;

EID: 37349116027     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.07.0207.0140     Document Type: Article

References (4)

1. S.R. Norsworthy, R. Schreier and G.C. Temes, Delta-Sigma Data Converters, IEEE Press, 1997, Sec. 14.4.2.
2. J. Silva, U. Moon, J. Steensgaard, and G.C. Temes, "Wideband Low-Distortion Delta-Sigma ADC Topology," Electronics Letters, vol. 37, no. 12, 2001, pp. 737-738.
3. S.C. Lee, Y.D. Jean, J.K. Kwon, "A 9-Bit 80-MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique," ETRI Journal, vol. 29, no. 3, June 2007, pp. 408410.
4. R. Gaggle et.al., "A 85 dB Dynamic Range Multi-Bit Delta-Sigma ADC for ADSL-CO Applications in 0.18 um CMOS," IEEE Journal of SoM-State Circuits, vol. 38, no. 72, 2003, pp. 355-358.