A 9-Bit 80-MS/s CMOS pipelined folding A/D converter with an offset canceling technique

ETRI Journal

Volumn 29, Issue 3, 2007, Pages 408-410

  Lee, Seung Chul ^a   Jeon, Young Deuk ^a   Kwon, Jong Kee ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Analog to digital converter (ADC); Folding

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; INTEGRAL EQUATIONS; INTEGRATED CIRCUIT LAYOUT;

DIFFERENTIAL NONLINEARITY; FOLDING ARCHITECTURE; INTEGRAL NONLINEARITY; OFFSET CANCELING TECHNIQUES;

ANALOG TO DIGITAL CONVERSION;

EID: 34250169377     PISSN: 12256463     EISSN: None     Source Type: Journal    
DOI: 10.4218/etrij.07.0206.0180     Document Type: Article

References (4)

1. K. Makigawa, K. Ono, T. Ohkawa, K. Matsuura, and M. Segami, "A 7-Bit 800-Msps 120-mW Folding and Interpolation ADC Using a Mixed-Averagmg Scheme', Proc.Symp. VISI Circuits, 2006,pp. 138-139.
2. G. Geelen and E. Paulus, "An 8-b 600-MS/s 200-mW CMOS Folding A/D Converter Using an Amplifier Preset Technique,"IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 254-255.
3. P] M.J. Choe, B.S. Song, and K. Bacrania, "A 13-b 40-Msanple/s CMOS Pipdined Folding ADC with Background Oflset Trimming," IEEE J. Solid-State Cicuits, vol 35, no. 12, Dec. 2000, pp. 1781-1790.
4. K. Kattmann and J. Barrow, "A Technique for Reducing Differential Non-linearity Error in Flash A/D Converter," IEEE ISSCC Dig. Tech. Papers, Feb. 1991, pp. 170-171.