Alteration of gate oxides thickness for SOC level integration

Materials Science in Semiconductor Processing

Volumn 12, Issue 3, 2009, Pages 99-105

  Sharma, Satinder K ^a   Prasad, B ^a   Kumar, Dinesh ^a   Raj kumar, ^a  

^a KURUKSHETRA UNIVERSITY   (India)

Author keywords

Alteration oxide thickness; C V; Dit and FTIR; J E

Indexed keywords

CIRCUIT DESIGNS; DESIGN FLEXIBILITY; ELECTRICAL BEHAVIORS; ENTIRE SYSTEM; FABRICATION TECHNOLOGIES; FLUORINE IMPLANTATION; FTIR; FTIR MEASUREMENTS; GATE OXIDE; INTERFACE STATE; OXIDATION RATES; OXIDE THICKNESS; PROCESS TECHNOLOGIES; SEMICONDUCTOR INDUSTRY; STOICHIOMETRIC COMPOSITIONS; SUB-SYSTEMS;

FLUORINE; FOURIER TRANSFORM INFRARED SPECTROSCOPY; GATES (TRANSISTOR); INNOVATION; MOS DEVICES; PROGRAMMABLE LOGIC CONTROLLERS; SEMICONDUCTOR DEVICE MANUFACTURE;

DIELECTRIC MATERIALS;

EID: 73049109053     PISSN: 13698001     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mssp.2009.08.003     Document Type: Article

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