A parallel 32×32 time-to-digital converter array fabricated in a 130 nm imaging CMOS technology

ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 196-199

  Gersbach, M ^a,e   Maruyama, Y ^e   Labonne, E ^a   Richardson, J ^b,c   Walker, R ^c   Grant, L ^b   Henderson, R ^c   Borghetti, F ^d   Stoppa, D ^d   Charbon, E ^a,e  

^a EPFL   (Switzerland)

^b STMicroelectronics Ltd Bristol   (United Kingdom)

^c UNIVERSITY OF EDINBURGH   (United Kingdom)

^d FONDAZIONE BRUNO KESSLER   (Italy)

^e DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

FLIM; SPAD; TCSPC; TDC; TDC array

Indexed keywords

3D IMAGING; CMOS TECHNOLOGY; FLUORESCENCE LIFETIME IMAGING MICROSCOPY; IMAGERS; INTEGRAL NONLINEARITY; TIME TO DIGITAL CONVERTERS; TIME-RESOLVED; TIMING RESOLUTIONS;

CMOS INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; THREE DIMENSIONAL; TIME MEASUREMENT;

ANALOG TO DIGITAL CONVERSION;

EID: 72849153263     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2009.5326021     Document Type: Conference Paper

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