Comparison of double patterning technologies in NAND flash memory with sub-30nm node

ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

Volumn , Issue , 2009, Pages 269-271

  Hwang, Byungjoon ^a   Han, Jeehoon ^a   Kim, Myeong Cheol ^a   Jung, Sunggon ^a   Lim, Namsu ^a   Jin, Sowi ^a   Yim, Yongsik ^a   Kwak, Donghwa ^a   Park, Jaekwan ^a   Choi, Jungdal ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

APPROPRIATE TECHNOLOGIES; BIT LINES; CELL TYPES; CHARGE TRAP; DEVICE CHARACTERISTICS; DOUBLE PATTERNING; E-BEAM LITHOGRAPHY; HIGH DENSITY; MASS PRODUCTION; MOS-FET; NAND FLASH MEMORY; NANO SCALE; PATTERNING TECHNOLOGY; POLY-SI GATES; PROCESS STEPS; SELF-ALIGNED;

MOSFET DEVICES; NAND CIRCUITS; NANOTECHNOLOGY; POLYSILICON; TECHNOLOGY;

FLASH MEMORY;

EID: 72849125125     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2009.5331401     Document Type: Conference Paper

References (7)

1. Donghwa Kwak, et al "Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory" VLSI Technology, pp. 12-13,2007
2. Yang-Kyu Choi, et al "A Spacer patterning technology for nanoscale CMOS" Electron Device, Vol 49, pp. 436-441, 2002
3. S. Zhang, et al "A novel sub-50nm poly-Si gate patterning technology" Electrical and Electronic Technology, Vol. 2, pp. 841-843,2001
4. Cahng-Hyun Lee, et al "Multi-Level NAND Flash Memory with 63nm Node TANOS(Si-Oxide-SiN-AI20 3-TaN) Cell Structure" VLSI Technology, pp. 21-22, 2006
5. Jangho Park, et al "Comparison ofSADP vs. R-SADP using Off-set spacer for Bit-line contacts of 76nm pitch on NAND Flash cell", ICMTD 2007
6. Byungjoon Hwang, et aI, "Development of Bit-Line Contact of 76nm pitch on NAND Flash Cell using Reversal PR and SADP Process", ASMC, pp. 356-358, 2007
7. Byungjoon Hwang, et aI, "Development of 38nm Bit-lines using Copper Damascene Process for 64-Giga bits NAND Flash", ASMC 2008