A novel sub-50 nm poly-Si gate patterning technology

IEEE Region 10 International Conference on Electrical and Electronic Technology

Volumn , Issue , 2001, Pages 841-843

  Zhang, Shengdong ^a,b   Chan, Mansun ^a   Han, Ruqi ^b   Liu, Xiaoyan ^b   Guan, Xudong ^b   Li, Ting ^b   Zhang, Dacheng ^b  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b PEKING UNIVERSITY   (China)

Author keywords

Edge defined; MOSFET; Patterning; Scaling

Indexed keywords

ELECTRON BEAM LITHOGRAPHY; MOSFET DEVICES; PHOTOLITHOGRAPHY; SCANNING ELECTRON MICROSCOPY;

GATE RESISTANCE;

POLYSILICON;

EID: 0035786563     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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