Multi-level NAND flash memory with 63 nm-node TANOS (Si-Oxide-SiN-Al 2O3-TaN) cell structure

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 21-22

  Lee, Chang Hyun ^b   Choi, Jungdal ^b   Kang, Changseok ^b   Shin, Yoocheol ^b   Lee, Jang Sik ^b   Sel, Jongsun ^b   Sim, Jaesung ^b   Jeon, Sanghun ^b   Choe, Byeong In ^b   Bae, Dukwon ^a   Park, Kitae ^b   Kim, Kinam ^b  

^a Semiconductor R and D Center   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING; ELECTRIC LOSSES; LOGIC DESIGN; NAND CIRCUITS; SILICON COMPOUNDS;

CHARGE TRAPPING MEMORY CELLS; TANOS CELLS;

FLASH MEMORY;

EID: 41149168755     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. K. Kim, et al, VLSI-TSA-TECH., pp. 88-94, 2005.
2. C. H. Lee, et al, IEDM Tech. Dig., pp. 613-616, 2003.
3. Y. C. Shin, et al, IEDM Tech. Dig., pp. 337-340, 2005.