SCOPUS 정보 검색 플랫폼

European Microwave Week 2009, EuMW 2009: Science, Progress and Quality at Radiofrequencies, Conference Proceedings - 4th European Microwave Integrated Circuits Conference, EuMIC 2009

Volumn , Issue , 2009, Pages 65-68

90nm node RF CMOS technology with latch-up immunity on high-resistivity substrate

(8) Momo, N a Higashi, Y a Oda, M a Matsuzawa, K a Kokubun, K a Ohguro, T a Momose, H S a Toyoshima, Y a

a TOSHIBA CORPORATION (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

90NM NODE; BASE RESISTANCE; EMITTER INJECTION; HIGH-Q INDUCTORS; HIGH-RESISTIVITY SUBSTRATE; INJECTION MODE; LATCH-UPS; LOW LOSS; MEASUREMENT AND SIMULATION; RF CMOS TECHNOLOGY; RF-CMOS; SI SUBSTRATES; SUBSTRATE NOISE; SWITCHING CURRENTS; TRANSMISSION LINE;

CMOS INTEGRATED CIRCUITS; DEGRADATION; INTEGRATED CIRCUITS; ION BOMBARDMENT; ION IMPLANTATION; MICROWAVE INTEGRATED CIRCUITS; MICROWAVES; NANOTECHNOLOGY; OPTICAL RESOLVING POWER;

SUBSTRATES;

EID: 72449156518 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (4)

References (6)

1
- 51849096908
- Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SoC) application
- June
- T. Ohguro, K. Kojima, N. Momo, H. S. Momose, and Y. Toyoshima, "Process dependence of 0.11 μm RF CMOS on high-resistivity substrate for System on Chip (SoC) application" RFIC. Dig., pp.559-562, June 2008.
- (2008) RFIC. Dig , pp. 559-562
- Ohguro, T.¹ Kojima, K.² Momo, N.³ Momose, H.S.⁴ Toyoshima, Y.⁵

2
- 0036045163
- Improvement of high resistivity substrate for future mixed analog-digital application
- June
- T. Ohguro, K. Kojima, H. S. Momose, S. Nitta, T. Fukuda, T. Enda and Y. Toyoshima, "Improvement of high resistivity substrate for future mixed analog-digital application" VLSI Symp. Dig., pp158-159, June 2002.
- (2002) VLSI Symp. Dig , pp. 158-159
- Ohguro, T.¹ Kojima, K.² Momose, H.S.³ Nitta, S.⁴ Fukuda, T.⁵ Enda, T.⁶ Toyoshima, Y.⁷

3
- 18344405850
- 0.1μm RF CMOS on high resistivity substrates for system on chip (SOC) application
- Dec
- J-Y Yang, K. Benaissa, D. Crenshaw, B. Williams, S. Sridhar, J. Ai, G. Boselli, S. Zhao, S-P Tang, N. Mahalingam, S. Ashburn, P. Madhani, T. Blythe and H. Shichijo, "0.1μm RF CMOS on high resistivity substrates for system on chip (SOC) application," IEDM. Dig., pp.667-670, Dec. 2002.
- (2002) IEDM. Dig , pp. 667-670
- Yang, J.-Y.¹ Benaissa, K.² Crenshaw, D.³ Williams, B.⁴ Sridhar, S.⁵ Ai, J.⁶ Boselli, G.⁷ Zhao, S.⁸ Tang, S.-P.⁹ Mahalingam, N.¹⁰ Ashburn, S.¹¹ Madhani, P.¹² Blythe, T.¹³ Shichijo, H.¹⁴

4
- 57749181543
- Double Thick Copper BEOL in Advanced HR SOI RF CMOS Technology: Integration of High Performance Inductors for RF Front End Module
- Oct
- C. Pastore, F. Gianesello, D. Gloria, E. Serret, P. Bouillon, B. Rauber, and Ph. Benech. "Double Thick Copper BEOL in Advanced HR SOI RF CMOS Technology: Integration of High Performance Inductors for RF Front End Module" SOI Conf. Dig., pp137-138, Oct. 2008.
- (2008) SOI Conf. Dig , pp. 137-138
- Pastore, C.¹ Gianesello, F.² Gloria, D.³ Serret, E.⁴ Bouillon, P.⁵ Rauber, B.⁶ Benech, P.⁷

5
- 0032272978
- M. Nandakumar, A. Chatterjee, S. Sridhar, K. Joyner, M. Rodder, I.-CChen, Shallow trench isolation for advanced ULSI CMOS technologies IEDM. Dig., pp.133-136, 1998.
- M. Nandakumar, A. Chatterjee, S. Sridhar, K. Joyner, M. Rodder, I.-CChen, "Shallow trench isolation for advanced ULSI CMOS technologies" IEDM. Dig., pp.133-136, 1998.

6
- 84886447975
- A shallow trench isolation for sub-0.13 μm CMOS technologies
- M. Nandakumar, et al., "A shallow trench isolation for sub-0.13 μm CMOS technologies," IEDM. Dig., pp.657 -660, 1997.
- (1997) IEDM. Dig , pp. 657-660
- Nandakumar, M.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.