Platinum silicide metallic source & drain process optimization for FDSOI pMOSFETs

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2009, Pages

  Carron, V ^a   Nemouchi, F ^a   Morand, Y ^b   Poiroux, T ^a   Vinet, M ^a   Bernasconi, S ^b   Louveau, O ^b   Lafond, D ^a   Delaye, V ^a   Allain, F ^a   Minoret, S ^a   Vandroux, L ^a   Billon, T ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER DEPOSITION; DRAIN PROCESS; GATE LENGTH; P-MOSFETS; PLATINUM SILICIDES; PMOS FET DEVICES; SOURCE AND DRAINS; SPECIFIC CONTACT RESISTIVITY;

OPTIMIZATION; PLATINUM; SILICIDES; SURFACE CLEANING;

MOSFET DEVICES;

EID: 72449152753     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2009.5318748     Document Type: Conference Paper

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