TSV and 3D wafer bonding technologies for advanced stacking system and application at ITRI

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 70-71

  Lo, Wei Chung ^a   Chen, Yu Hua ^a   Ko, Cheng Ta ^a   Kao, Ming Ger ^a  

^a Bldg 17 ^*  (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTERCONNECTS; 3D STACKING; BONDING TECHNOLOGY; CHIP STACKING; CHIP THICKNESS; CORE COMPETENCE; FABRICATION TECHNOLOGIES; HIGH RELIABLE; INTERCONNECT RELIABILITY; INTERCONNECT TECHNOLOGY; LOW COSTS; LOW RESISTANCE; LOWER COST; MECHANICAL STUDY; MICROBUMPING; RELIABILITY TEST; STACKED SYSTEMS; STACKING SYSTEMS; TEST VEHICLE; THERMAL CYCLING TEST; THERMAL DISSIPATION; THROUGH HOLE; VOID-FREE; WAFER STACKING; WAFERBONDING TECHNOLOGY;

COMPUTER CRIME; FLIP CHIP DEVICES; RELIABILITY; TECHNOLOGY; THREE DIMENSIONAL;

WAFER BONDING;

EID: 71049180343     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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2. K. Takahashi, et al., "Current Status of Research and Development for Three-Dimensional Chip Stack Technology," Jpn. J. Appl. Phys., Vol. 40, No.4 B(2001), pp.3032-3037.
3. P. Ramm, et al., "Three dimensional metallization for vertically integrated circuits, " Microelectron. Eng., Vol. 3738 (1997), pp.39-47.
4. rd Electronic Components and Technology Conf, New Orleans, Louisiana, May. 2003, pp. 1147-1152.
5. th Electron. Components and Technology Conference, Orlando, Fl, USA, May 2008