Comprehensive design methodology of dopant profile to suppress gate-LER-induced threshold voltage variability in 20nm NMOSFETs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 146-147

  Fukutome, H ^a,d   Hori, Y ^b   Sponton, L ^c   Hosaka, K ^a   Momiyama, Y ^a   Satoh, S ^a   Gull, R ^c   Fichtner, W ^d   Sugii, T ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

^b Fujitsu Quality Laboratory   (Hong Kong)

^c SYNOPSYS SWITZERLAND LLC   (Switzerland)

^d ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

3D SIMULATIONS; CARRIER PROFILING; COMPREHENSIVE DESIGNS; DOPANT PROFILE; EFFECTIVE CHANNEL LENGTH; GATE WIDTH DIRECTION; LATERAL EXTENSION; NMOSFETS; P-MOSFETS; THRESHOLD VOLTAGE VARIABILITY;

ELECTRIC BREAKDOWN; THREE DIMENSIONAL COMPUTER GRAPHICS; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 71049116031     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. J. Kuhn, Tech. Dig. IEDM 2007, p.471.
2. A. Asenov, et al., T-ED 50, p.1837 (2003).
3. H. Fukutome, et al., T-ED 53, p. 2755 (2006).
4. F. Arnaud, Tech. Dig. IEDM 2008, p.633.
5. S. Hasegawa, Tech. Dig. IEDM 2008, p.938.