Speeding up simulation of systemc using model checking

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5902 LNCS, Issue , 2009, Pages 1-16

  Blanc, Nicolas ^a   Kroening, Daniel ^b  

^a ETH ZURICH   (Switzerland)

^b UNIVERSITY OF OXFORD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CONCURRENT SYSTEMS; CONTEXT SWITCH; DESIGN FLAWS; FORMAL ANALYSIS; MODEL CHECKER; MODEL-CHECKING TECHNIQUES; ORDER OF MAGNITUDE; PARTIAL-ORDER REDUCTION; RUNTIMES; SIMULATION SPEED-UP; SYSTEM-LEVEL MODELING; SYSTEMC; THREAD SCHEDULING;

FORMAL METHODS; LOGIC DESIGN; PROGRAM COMPILERS; SIMULATORS;

MODEL CHECKING;

EID: 70649102905     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-10452-7_1     Document Type: Conference Paper

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