Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Horibe, Akihiro ^a   Yamada, Fumiaki ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

3D chip stack; Fine pitch interconnection; Inter chip fill; Stack joining process; Thin chip; Through silicon vias

Indexed keywords

FINE PITCH; INTER-CHIP; JOINING PROCESS; THIN CHIPS; THROUGH SILICON VIAS;

INTERCONNECTION NETWORKS; JOINING;

THREE DIMENSIONAL;

EID: 70549098151     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306555     Document Type: Conference Paper

References (4)

1. Claudius Feger, et al., "The Over-Bump Applied Resin Wafer-Level Underfill Process: Process, Material and Reliability" ECTC 2009 proceeding, pp. 1502, (2009)
2. Keiji Matsumoto, Yoichi Taira, " Thermal Resistance Measurement if Interconnections, for the Investigation of the Thermal Resistance of a Three-dimentional (3D) Chip Stack", SEMI-THERM, pp.321-328 (2009)
3. J.U. Knickerbocker et al., "3D Silicon Integration", 58th Electronic Components and Technology Conference, pp.538-543 (2008)
4. Akihiro Horibe, Fumiaki Yamada, "Inter Chip Fill for 3D Chip Stack", ICEP2009 proceeding, pp. (2009)