Through silicon via(TSV) defect/pinhole self test circuit for 3D-IC

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Tsai, Menglin ^a   Klooz, Amy ^a   Leonard, Alexander ^a   Appel, Jennie ^a   Franzon, Paul ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TEST; EMERGING TECHNOLOGIES; OXIDE DEPOSITION; SELF TEST; THROUGH-SILICON-VIA;

ANALOG CIRCUITS;

THREE DIMENSIONAL;

EID: 70549083734     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306569     Document Type: Conference Paper

References (4)

1. Andry, P. S., C. K. Tsang, B. C. Webb, E. J. Sprogis, S. L. Wright, B. Dang, and D. G. Manzer. 2008. "Fabrication and characterization of robust through-silicon vias for silicon-carrier applications." IBM Journal of Research & Development 52, no. 6: 571-581. Computers & Applied Sciences Complete, EBSCOhost (accessed May 18, 2009)
2. Eaton, B., Kumar, A., Pamarthy, S., "Deep silicon etch for TSVs with improved via profile/process control," Solid State Technology; Apr2009, Vol. 52 Issue 4, p22-25, 3p.
3. Jang' M. D., Ryul* C., Lee Y. K., Cho H. B., Kiml J., Oh S. T, Lee J. W. , Yu' J., "Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)," Electronic Components and Technology Conference, 2007.
4. Lietaer N., Storås P., Breivik L., Moe S., "Development of cost-effective highdensity through-wafer interconnects for 3D Microsystems, " Journal of Micromechanics and Microengineering, Issue 6, June 2006.