Automatic generation of fast timed simulation models for operating systems in SoC design

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 620-627

  Yoo, Sungjoo ^a   Nicolescu, Gabriela ^a   Gauthier, Lovic ^a   Jerraya, Ahmed A ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC GENERATION; EQUIVALENCE PROBLEM; INSTRUCTION SET SIMULATORS; ON CHIP COMMUNICATION; ORDERS OF MAGNITUDE; SIMULATION ENVIRONMENT; SIMULATION SPEED-UP; VIRTUAL PROCESSOR;

EQUIVALENCE CLASSES; EXHIBITIONS; MICROPROCESSOR CHIPS;

COMPUTER SIMULATION;

EID: 70450270980     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998365     Document Type: Conference Paper

References (23)

1. K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on- Chips", Proc. Design Automation Conf., pp. 513-518, June 2000.
2. AMBA Specification, ARM Ltd. Hall.
3. Sonics, Inc., "Silicon Backplane μNetwork", available at http://www.sonicsinc.com/Pages/Networks.html.
4. J. A. J. Leijten et al., "PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia", Proc. Int'l Conference on Computer Design, 1997.
5. P. Guerrier and A. Greiner, "A Generic Architecture for On-Chip Packet-Switched Interconnections", Proc. Design Automation and Test in Europe, 2000.
6. W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks", Proc. Design Automation Conf., 2001.
7. L. Gauthier, S. Yoo, and A. A. Jerraya, "Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software", Proc. Design Automation and Test in Europe, Mar. 2001.
8. C. K. Lennard, P. Schaumont, G. de Jong, A. Haverinen, and P. Hardee, "Standards for System-Level Design: Practical Reality or Solution in Search of a Question?", Proc. Design Automation and Test in Europe, pp. 576-585, Mar. 2000.
9. D. Lyonnard, S. Yoo, A. Baghdadi, and A. A. Jerraya, "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip", Proc. Design Automation Conf., June 2001.
10. K. Lahiri, A. Raghunathan, and S. Dey, "Efficient Exploration of the SoC Communication Architecture Design Space", Proc. Int'l Conf. on Computer Aided Design, pp. 424 - 430, Nov. 2000.
11. E. Verhulst, "From a distributed embedded RTOS to a programatic framework for multi-core SoC", MP SoC school, Aix-les-Bains, France, July 2001.
12. Synopsys, Inc., "CoCentric SystemC Compiler", available at http://www.synopsys.com/.
13. Coware, Inc., "N2C", available at http://www.coware.com/ cowareN2C.html.
14. WindRiver Systems, Inc., "VxWorks 5.4", available at http://www.wrs.com/products/html/vxwks54.html.
15. D. Desmet, D. Verkest, and H. De Man, "Operating System Based Software Generation for Systems-on-Chip", Proc. Design Automation Conf., June 2000.
16. "CarbonKernel", available at http://www.carbonkernel.org/.
17. Cadence Design Systems, Inc., Virtual Component Codesign.
18. S. Yoo, G. Nicolescu, D. Lyonnard, A. Baghdadi, and A. A. Jerraya, "A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design", Proc. Int'l Workshop on Hardware-Software Codesign, 2001.
19. D. Jaggar, Advanced RISC Machines Architectural Reference Manual, Prentice Hall, July 1996.
20. J. Cockx, "Efficient Modeling of Preemption in a Virtual Prototype", Proc. IEEE International Workshop on Rapid System Prototyping, June 2000.
21. M. Lajolo, M. Lazarescu, and A. Sangiovanni-Vincentelli, "A Compilation-based Software Estimation Scheme for Hardware/ Software Co-Simulation", Proc. Int'l Workshop on Hardware- Software Codesign, May 1999.
22. K. Suzuki and A. Sangiovanni-Vincentelli, "Efficient Software Performance Estimation Methods for Hardware/Software Codesign", Proc. Design Automation Conf., June 1996.
23. Synopsys, Inc., "SystemC, Version 2.0", available at http://www.systemc.org/.